Characterization of STI Edge Effects on CMOS Variability

Wils, Nicole; Tuinhout, H.P.; Meijer, Maurice

doi:10.1109/tsm.2008.2010731

Cited by 29 publications

(14 citation statements)

References 6 publications

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“…Also note that, although small, the effect is opposite to the effect observed for the NMOS devices: in case of PMOS the strained device (T 2 ) has a higher current factor (higher mobility) than the unstrained device (T 1 ). Note the similarity with the impact of STI stress [1]. Furthermore, the effect is reduced or again even reverses sign at 125°C.…”

Section: 4/4 Nmos Vb'ee [%]supporting

confidence: 55%

“…The number of measured pairs on the wafer (population size) was 119. A complete voltage sweep allows us to generate so called mismatch sweeps, showing the relative drain current mismatch median and standard deviation (P_'I d /I d and V_'I d /I d ) as a function of gate voltage [1]. These sweeps immediately reveal a possible effect on the drain current (offset as well as fluctuations) in different operating regions, going from weak to strong inversion.…”

Section: Discussionmentioning

confidence: 99%

“…Extreme care was taken to assure that all possible (undesired) effects due to asymmetric metallization layout and unequal access resistances are avoided. Also note the relatively large separation between the STI edge and the gated area to mitigate STI stress effects [1]. A special set of matched pair test structures is used for this metal coverage study.…”

Section: Test Structures and Analysismentioning

confidence: 99%

“…Design for good matching not only requires that the transistor area is optimized to obtain required matching, but also the complete layout of the devices should be identical in order to avoid systematic mismatch effects (e.g. due to a difference in well proximity effect or STI stress effect in case of MOS transistors [1,2]). Moreover, the environment near matched devices should be as symmetrical as possible.…”

Section: Introductionmentioning

confidence: 99%

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Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Wils

Tuinhout

Meijer

2010

2010 International Conference on Microelectronic Test Structures (ICMTS)

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This paper summarizes a comprehensive study on the effect of asymmetrical metal coverage on matching performance for a 45 nm copper damascene based CMOS process. We demonstrate that random mismatch fluctuations are not affected by metal layout asymmetries and we provide valuable new insights about the magnitude of systematic mismatches that can be expected due to asymmetrical layouts and CMP tiling. For the first time we also present results on the impact of temperature increases on both systematic as well as random drain current mismatches.

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Section: 4/4 Nmos Vb'ee [%]supporting

confidence: 55%

Section: Discussionmentioning

confidence: 99%

Section: Test Structures and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Wils

Tuinhout

Meijer

2010

2010 International Conference on Microelectronic Test Structures (ICMTS)

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“…For 90 nm and below, layout effects such as well proximity effect (WPE) and shallow-trench isolation (STI) stress will result in bias-point shifts of 20-30% in analog circuits [7]. It is shown in [8] that though STI-stress causes large deviation in drain current and threshold voltage, it does not contribute to random mismatch. Inaccuracies in the photolithographic process will cause random variations in the dimensions of the active and passive components on the chip.…”

Section: Process Variationsmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

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Analysis of time delay difference due to parametric mismatch in matched filter channels

Stuarts

Julián

2014

Circuit Theory & Apps

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SUMMARYThis paper presents an analysis of the time delay difference between the outputs of two matched filter channels, in the presence of parametric mismatch. A theorem for computing the cross-correlation value between two signals is developed. From the cross-correlation theorem, expressions are developed that estimate the effect of parametric mismatch in the differential time delay (DTD) for filters of arbitrary type and order and input signals of arbitrary form. The accuracy of these expressions is simulated and then demonstrated experimentally using a carefully designed setup. Filter design considerations that attempt to minimize spurious DTD in high-precision time delay estimation systems are presented.

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Characterization of STI Edge Effects on CMOS Variability

Cited by 29 publications

References 6 publications

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Analysis of time delay difference due to parametric mismatch in matched filter channels

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