Characterization of sidewall defects in selective epitaxial growth of silicon

Abstract

Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth isolation for advanced ultralarge scale integrationThe sidewall defects in high quality selective epitaxial growth ͑SEG͒ of silicon were characterized. Three different SEG diode structures were fabricated and the bulk and perimeter defects were characterized through electrical measurements and transmission electron microscopy ͑TEM͒. The structures investigated were SEG grown in a 1.2 m thick wet-etched field oxide, SEG grown in 1.2 m thick reactive-ion etched field oxide, and SEG grown in a 1.2 m high and 0.3 m wide sidewall oxide cavity. The thin sidewall oxide cavity SEG diode showed the best ideality factors and minimum saturation current densities for diodes intersecting the sidewall, indicating the least thermal stress generated at the SEG/oxide sidewall interface during the cool-down period. Cross-sectional TEM micrographs showed no defects in the bulk SEG or at the sidewall, indicating that the thermal stress in all the processes was not high enough to cause plastic deformation, dislocations, or stacking faults.

Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth isolation for advanced ultralarge scale integration

“…The OX-5 control diodes exhibited ideal current-voltage characteristics and were as good as pϩ/n junction diodes reported earlier in selective epitaxial growth studies. [11][12][13] Hence, when the junctions were 5 m away from the sidewall or when the field insulator is nitrided, the reverse saturation current density ͑both total and the perimeter component͒ were about the same. These reverse and forward measurements clearly show the improvement and reduction in the sidewall leakage currents due to the presence of the nitrided field oxide, thus proving the fact that the presence of the nitrided field oxide does reduce the thermal induced defects and hence the leakage currents.…”

“…The main cause of these defects has been demonstrated to be coefficient of thermal expansion ͑CTE͒ mismatch induced by thermal stress during the cooldown period of the epitaxial growth. 13,14 The detrimental effects of these defects can be circumvented if the defective sidewall region is implanted and is encompassed well within a junction. This is the case for bipolar junction transistors where, for most device layouts, the extrinsic base region intersects the sidewall of the oxide isolation region as shown in Fig.…”

“…In addition, the process is also cost effective when compared to shallow trench isolation. 13 The only hindrance is the formation of these defects when the growth is done at high temperatures. A theoretical understanding and a one-dimensional model have been developed which explain that the defects are generated when the thermal stress induced from the sidewall and corner region of the oxide exceeds the yield strength of silicon, resulting in plastic deformation.…”

On the design of piezoresistive silicon cantilevers with stress concentration regions for scanning probe microscopy applications

“…The fabrication of ultra thin cantilevers is ideally suited using silicon-on-insulator (SOI) technology [19]. The structure with reduced thickness for the SCR can be fabricated using selective epitaxial growth (SEG) of silicon and chemicalmechanical polishing [20]. Figures 13(a)-(g) show the process sequence for such a process where SEG is ideally suited for fabricating these structures since the silicon can be grown over topography and steps, that are created within the underlying oxide film.…”

Laser-Induced Epitaxial Growth Technology for Monolithic Three Dimensional Integrated Circuits

“…3 On the other hand, fabrication of a perfect single crystal on an oxide using continuous lasers or heated graphite strips is possible; whose quality is comparable to bonded silicon-on-oxide wafers. 4 However, this is not a proper stack technology; because the junction area of the underlying devices will be degraded by high temperature substrate heating during the process. Although solid phase epitaxy (SPE) can be easily acquired by using a simple furnace, Si films crystallized with long annealing times (>6 hr) at low temperatures (∼600 • C) contain defects such as stacking faults and micro-twins which may result in limited success of stacked devices by sub-threshold leakage, decreased on/off ratio and broad current distribution.…”