Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

Inoue, Fumihiro; Jourdain, Anne; Vos, Joeri De; Sleeckx, Erik; Beyne, Eric; Patel, Jash; Ansell, Oliver; Ashraf, Huma; Hopkins, Janet; Thomas, Dave; Uedono, Akira

doi:10.1109/ectc.2016.102

Cited by 17 publications

(3 citation statements)

References 7 publications

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“…The TSV-last process can be adapted for extreme thinning [10]. The basic processing for TSV-last includes lithography, TSV etch, oxide liner deposition, bottom liner opening, barrier and seed deposition, Cu plating, and chemical mechanical planarization (CMP) [1].…”

Section: Tsv Manufacturing and Cost Implicationsmentioning

confidence: 99%

“…This assumption is removed later where signal multiplexing is considered and the related circuits are assumed to occupy this area. The stacking yield 𝑌 𝑠𝑡𝑎𝑐𝑘𝑖𝑛𝑔 and the total cost 𝐶 𝑡𝑜𝑡𝑎𝑙 for 𝑁 -layer inductive link based 3-D ICs is the same as ( 8) and (10), respectively.…”

Section: Inductor Area and Cost Predictionmentioning

confidence: 99%

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Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Jiang

Papistas

Pavlidis

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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Contactless three-dimensional (3-D) interconnects have been proposed as an alternative to through-silicon via (TSV) due to its manufacturing compatibility with two-dimensional (2-D) processes. Typically, contactless 3-D circuits are thought to require considerable silicon resources compared to TSV. However, recent manufacturing options, such as extreme wafer thinning, provide new opportunities for this approach. This paper, therefore, explores these opportunities for producing 3-D systems of lower cost. The presented cost analysis and models usefully combine fabrication cost with performance requirements for inter-tier communication as a critical component of 3-D systems. Thus, benchmark circuits are simulated for a two-tier system using a commercial 65 𝑛𝑚 technology and communicating at a data rate of 1 𝐺𝑏𝑝𝑠 per link, although the model is directly applicable to any technology or design specifications. Interestingly, inductive links can be a useful alternative to TSV for specific and expected manufacturing capabilities. Furthermore, the effectiveness of different multiplexing schemes and their effect on system cost is also evaluated. CCS CONCEPTS• Hardware → 3D integrated circuits; Radio frequency and wireless interconnect.

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Section: Tsv Manufacturing and Cost Implicationsmentioning

confidence: 99%

Section: Inductor Area and Cost Predictionmentioning

confidence: 99%

Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Jiang

Papistas

Pavlidis

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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“…Whilst either thinning method can adequately remove the excess material, grinding can remove material at a faster rate than dry etching, but the final wafer thickness is more difficult to control. Testing has shown that grinding causes a damaged layer roughly 200nm thick that has large compressive stress leading to a concavely bowed substrate that requires an additional stress relief process when the griding is complete [33]. Dry etching is a slower method of material removal but it typically has an improved surface roughness value and chip strength is up to 50% greater after the process is completed, as stress is not introduced into the substrate during thinning, there is no requirement for a stress relief step at the end of the process [34].…”

Section: Two Stage Undercut Removal Methodsmentioning

confidence: 99%

Investigation into the manipulation of non-uniformity and undercut features of a positive profile through silicon via

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The key enabling technology for 2.5D and 3D packaging applications is the through silicon via (TSV), this device allows integrated circuits and additional component layers to be vertically stacked, this minimises internal signalling lengths allowing for faster operation, reduced heat production and lower power consumption. TSV’s are commonly formed with a positive profile structure which minimises conductor deposition defects in downstream production stages. This research was carried out on an SPTS Technologies Ltd Pegasus™ deep silicon etcher employing a single step O2/SF6/Ar process. The aim was to identify a predictable set of process parameters that can be used manipulate the dimensions of the ‘undercut’ feature that regularly forms at the top of the TSV profile during dry plasma etch processing. An L16 (4^5) Taguchi Array was used to determine the interaction effects of changing five critical process parameters on the undercut feature dimensions. The results from the process sample runs were analysed using commercially available statistical analysis software to investigate any predictable interactions between process parameter values and TSV profile dimensions. The outcome showed that there were no relationships that would facilitate predictable manipulation of the undercut dimensions. However, a clear and predictable trend was observed from the results which showed that increasing the wafer platform temperature results in a decrease in across wafer non-uniformity of critical TSV profile dimensions.

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