Characterization of electroplated copper films for three-dimensional advanced packaging

Abstract

A study was carried out to determine the feasibility of using the Cu electroplating process to achieve good gap fill in interchip-via ͑ICV͒ wafers, focusing on the effect different current wave forms have on electroplated Cu film properties, the gap fill capability and the chemical mechanical planarization process. It was found that the roughness of direct current ͑dc͒-plated Cu films is at least three times lower than that of pulse-plated films and the roughness of the latter was observed to be strongly dependent on the magnitude of forward (I f ) and reverse (I r ) currents. This produced a significant difference in reflectivity between the two types of films. The as-deposited dc-and pulse-plated Cu films were also found to have specific resistivities of ϳ2.2 and ϳ2.1 ⍀ cm, respectively. They were reduced to a similar value of 1.77 ⍀ cm after annealing at 200°C. All the dc and higher I f pulse-plating processes produced Cu films having an average polish rate of 7000 Å/min with the polish rate U% less than 3%, showing a fluctuating profile across the wafer. The higher I r pulse-plated film showed a very low polish rate of 210 Å/min with the polish rate U% at 58%, resulting in a dome profile. The multistep dc plating process was found unsuitable for the filling of large vias in the ICV wafers as it resulted in conformal plating with a large center seam being seen due to the pinch-off effect at the top of the via. The pulse-plating process showed a significant improvement in the gap fill capability with a reduction in the size of the center void. The pinch-off effect was also greatly reduced when higher I r was used and an increase in bottom coverage could also be seen, resulting in acceptable gap fill with only a small center void in the ICV wafers.

Comparison of the sputter rates of oxide films relative to the sputter rate of SiO2

“…However, in most circumstances there they found an offset at zero thickness. 25 This result suggests that without the offset correction identified by Seah, there can be a systematic variation or deviation in the sputter rate comparison to the SiO 2 reference films. Since the magnitude of this offset might contribute as much as 5% varia-tion in the sputter rates observed for our thinnest reference oxides, we made a set of measurements comparing the sputter rates for SiO 2 films of differing thicknesses as measured by ellipsometry ͑nominally 17, 60, and 100 nm͒.…”

“…[22][23][24] As part of that work it has been noted that many different methods of measuring oxide thickness produce a linear behavior with oxide thickness. 25 suggest that for a silicon wafer with no preheat treatment this offset may be as large as 1.2 nm. These offsets may be of roughly 1 nm in magnitude for ellipsometry ͑ϳ1 nm͒ and x-ray reflectance measurements ͑ϳ0.55 nm͒.…”

Mechanical and electrical properties of electroplated copper for MR-imaging coils

“…In state-of-the-art IC technology copper is used for electrical interconnections with high electrical conductivity and good via-filling (Miura and Honma 2003;Seah et al 2004;Takahashi and Gross 1999).…”

Influence of contamination layer on thickness evaluation by X‐ray reflectometry

“…Typical polymer densities are approximately 1 g cm −3. [12] In the earlier stages of surface contamination, if the d contami is 0.5 g cm −3 , almost a quarter of the actual thickness of the contamination layer is introduced into the determined SiO 2 thickness, and this value should be considered as an uncertainty component. When the density of the contamination layer is small and it is extremely thin, it can be difficult to quantify its physical structures using XRR.…”