Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

Banzhaf, Christian T.; Grieb, Michael; Trautmann, Achim; Bauer, Anton J.; Frey, L.

doi:10.4028/www.scientific.net/msf.740-742.691

Cited by 7 publications

(8 citation statements)

References 6 publications

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“…Next, the oxide layer is formed by the thermal oxidation and PECVD method ( Fig. 2(d)) [15]. Finally, the trench is filled with polysilicon as shown in Fig.…”

Section: Fabrication Procedures and Parametersmentioning

confidence: 99%

An Improved 4H-SiC Trench MOS Barrier Schottky Diode With Lower On-Resistance

Cao

Bao

Wu³

et al. 2019

IEEE Access

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An improved 4H-SiC trench MOS barrier Schottky (TMBS) structure that can significantly reduce the specific on-resistance (R on,sp) is proposed in this paper. Compared with the conventional TMBS structure, an N-type region is added around the P+ shielding region and along the trench sidewall in the proposed structure, and the doping concentration is higher than that of the drift region. The JFET resistance, and spread resistance can both be reduced significantly during the forward bias to produce a much lower R on,sp , which have been verified through the numeric simulations and modeling analysis. The critical parameters (N-type region width and its doping concentration) of the proposed structure are mainly optimized by the ATLAS simulation tool. As a result, the breakdown voltage and leakage current of the improved structure remain basically unchanged compared with the conventional TMBS. However, the R on,sp and FoM (BV 2 /R on,sp) can be effectively improved by 41.9% and 70.9%, respectively. INDEX TERMS 4H-SiC, TMBS, JFET, analytical model, specific ON-resistance, electric field.

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“…Next, the oxide layer is formed by the thermal oxidation and PECVD method ( Fig. 2(d)) [15]. Finally, the trench is filled with polysilicon as shown in Fig.…”

Section: Fabrication Procedures and Parametersmentioning

confidence: 99%

An Improved 4H-SiC Trench MOS Barrier Schottky Diode With Lower On-Resistance

Cao

Bao

Wu³

et al. 2019

IEEE Access

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“…Trench gate MOSFETs (UMOSFETs) have successfully improved the trade-off relationship of static characteristics in comparison with planar MOSFETs (VDMOSFETs). This is because UMOSFETs have higher channel density and mobility than VDMOSFETs owing to the vertical channels formed in the trench sidewalls and the reduced cell pitch [5][6][7][8][9]. However, * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

High performance 4H-SiC MOSFET with deep source trench

Na¹,

Cheon²,

Kim³

2022

Semicond. Sci. Technol.

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In this study, we invesitaged a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom P+ shielding region. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

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“…Among SiC MOSFET structures, the trench MOSFET has a low channel resistance thanks to its high channel density and mobility [5,6] . However, in a high-voltage SiC MOSFET (a voltage of 3.3 kV or above), the channel resistance does not have a significant effect because of the high drift resistance.…”

Section: Introductionmentioning

confidence: 99%

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

Cha

Kim

2021

J. Semicond.

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In this paper, a 4H-SiC DMOSFET with a source-contacted dummy gate (DG-MOSFET) is proposed and analyzed through Sentaurus TCAD and PSIM simulations. The source-contacted MOS structure forms fewer depletion regions than the PN junction. Therefore, the overlapping region between the gate and the drain can be significantly reduced while limiting R ON degradation. As a result, the DG-MOSFET offers an improved high-frequency figure of merit (HF-FOM) over the conventional DMOSFET (C-MOSFET) and central-implant MOSFET (CI-MOSFET). The HF-FOM (R ON×Q GD) of the DG-MOSFET was improved by 59.2% and 22.2% compared with those of the C-MOSFET and CI-MOSFET, respectively. In a double-pulse test, the DG-MOSFET could save total power losses of 53.4% and 5.51%, respectively. Moreover, in a power circuit simulation, the switching power loss was reduced by 61.9% and 12.7% in a buck converter and 61% and 9.6% in a boost converter.

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Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

Cited by 7 publications

References 6 publications

An Improved 4H-SiC Trench MOS Barrier Schottky Diode With Lower On-Resistance

An Improved 4H-SiC Trench MOS Barrier Schottky Diode With Lower On-Resistance

High performance 4H-SiC MOSFET with deep source trench

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

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