Characterization of die stresses in flip chip on laminate assemblies using

Rahim, M. Kaysar; Sulding, J.C.; Copeland, D. Scott; Jaeger, R.C.; Lall, Pradeep; Johnson, Richard W.

doi:10.1109/ectc.2003.1216399

Cited by 3 publications

(1 citation statement)

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“…So underfill materials in use with products today are still of the 2 -phase capillary flow (impeded by low die to substrate stand -off and bump to bump clearance) variety. No matter which underfill type is used, when in use after cure, they transmit the mismatch stresses [11,12] to the increasingly fragile outer layers of interconnect/dielectric systems on the device [13]. At the lower end of operating temperatures (further below Tg, the glass transition temperature) the shear stress at die to underfill interface can exceed the adhesion strength (15 MPa) of low-k dielectrics and cause damage to both ILD and conductors.…”

Section: Factors Affecting Joint Reliabilitymentioning

confidence: 99%

Evaluation of a low-cost column bump technology for fine-pitch flip chip and WLP

Gupta¹,

Kalle²,

Fria³

IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585)

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The use of conventional solder bump for flip chip interconnection is now quite widespread and much infrastructure has been invested in to support this technology. According to the 2003 ITRS roadmap by 2007 bump pitch of 80 um will be needed. The shrink of bump pitch is driven by migration to 90 um technology. The die to joint gap will also shrink proportionately and start causing problems in underfill flow as well as increase stress on the fragile low -k dielectrics on die face. Tin capped gold column bumps were developed over a decade ago for fine pitch (50 um) flip chip interconnection of gallium arsenide power amplifiers used in mobile phones. Similar technology has now been developed for silicon applications using solder capped nickel column bumps deposited over various under bump metallurgies.By varying the deposition process bump columns and solder caps of several diameter (50 to 100 um), aspect ratio and heights (5 to 40 um) were deposited. Two solder compositions, eutectic Pb -Sn for baseline and Sn -Ag -Cu were used. Bonding processes were varied to create both barrel and fillet shaped flip chip joints to organic boards. Stress distribution in flip chip joints of various geometries were estimated by modeling and extended to lifetime prediction. The test assemblies were stressed by thermal cycling and high temperature hold .In this paper the results of the ongoing reliability tests and a cost estimate for this new low -cost bump technology that addresses many of the shortcomings of the now standard solder bump technology will be discussed.

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Section: Factors Affecting Joint Reliabilitymentioning

confidence: 99%