Characterization of Defects in As-Implanted and Laser-Annealed Si Layer together with Electrical Properties of As Atoms

Shibata, Kenji; Inoue, Tomoyasu; Kashiwagi, M.

doi:10.1143/jjap.21.1111

Cited by 2 publications

(1 citation statement)

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“…However, the relaxation of the strained-SiGe layer due to the large thermal stress that is induced by MSA may make such a combination challenging. [8][9][10][11] This study elucidates high defect density that results from the combination of strained-SiGe and subsequent MSA processes. Under certain implantation conditions, the MSA process induced defects in the underlying Si and degraded device performance.…”

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The Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETs

Wang

Huang

et al. 2012

J. Electrochem. Soc.

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The formation of the induced defects in the underlying Si substrate from the interaction of the partly relaxed source/drain strainedSiGe layer and subsequent millisecond annealing (MSA) have been systematically explored. It could be found that implantation in the shallower region of the strained-SiGe layer did not form defects in the underlying Si because the remaining strained-SiGe layer was sufficiently thick to resist wafer bending in response to the MSA thermal stress. However, deeper medium-level implantation indeed destroyed the part of the pseudomorphic strained-SiGe and the remaining strained-SiGe was too thin to withstand a significantly compressive stress induced by MSA surface heating and larger coefficient of thermal expansion (CTE) for SiGe than it for Si. Then brittle silicon substrate suffered a great tensile stress to generate numerous defects into plastic deformation. During MSA cooling, the over-bending of the surface SiGe layer contracted more than Si substrate and further results in highly tensile bending. Consequently, high defect density in the underlying Si results in high junction leakage and wafer bending leads to photolithographic limitation. A new approach for modifying the implantation conditions was developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 32 nm PMOSFETs.

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confidence: 99%