Characterization of Al2O3/4H-SiC and Al2O3/SiO2/4H-SiC MOS structures

Abstract

Abstract. The paper presents the results of characterization of MOS structures with aluminum oxide layer deposited by ALD method on silicon carbide substrates. The effect of the application of thin SiO 2 buffer layer on the electrical properties of the MOS structures with Al 2 O 3 layer has been examined. Critical electric field values at the level of 7.5-8 MV/cm were obtained. The use of 5 nm thick SiO 2 buffer layer caused a decrease in the leakage current of the gate by more than two decade of magnitude. Evaluated density of trap states near the conduction band of silicon carbide in Al 2 O 3 /4H-SiC MOS is about of 1x10 13 eV -1 cm -2 . In contrast, the density of the trap states in the Al 2 O 3 /SiO 2 /4H-SiC structure is lower about of one decade of magnitude i.e. 1x1012 eV -1 cm -2 . A remarkable change in the MOS structure is also a decrease of density of electron traps located deeply in the 4H-SiC conduction band below detection limit due to using of the SiO 2 buffer layer.Key words: aluminum oxide, MOS, silicon carbide, 4H-SiC, high-κ dielectrics. Characterization of Al Experimental detailsMOS structures used in this study were fabricated on low-resistivity 4H-SiC substrates (n ~ 5×10 18 cm -3 ) with n-type (n ~ 5×10 ), 10 μm thick epitaxial layer. Prior to the MOS fabrication the substrates were cleaned in organic solvents and dipped in 10% HF solution to remove the native oxide. The nickel layer was sputtered on the backside and annealed (Ar, 1050°C) to form an ohmic contact. Two kinds of samples were fabricated. On one part of samples, 5 nm SiO 2 buffer layer was fabricated by PECVD using SiH 4 and N 2 O plasma. Afterwards, a 50 nm layer of Al 2 O 3 was deposited on all samples by ALD. Al 2 O 3 layers were deposited at 200°C using trimethylaluminium (TMA) and water vapor (H 2 O) as Al and O precursors, respectively. Finally, a top layer of Ti/Al gate electrode (φ = 200 µm) was deposited on top of Al 2 O 3 by sputtering and patterned by lift-off technique. A schematic sketch of fabricated Al 2 O 3 /4H-SiC and Al 2 O 3 /SiO 2 /4H-SiC structures is presented in Fig. 1.

SiC‐based analytical model for gate‐stack dual metal nanowireFETwith enhanced analog performance

“…SiC has high critical electric field and large energy band gap than silicon which results in minimizing leakage current and maximize the device performance 15 . Al 2 O 3 has excellent lattice match with SiC, high thermal stability, superior compatibility with 4H‐SiC, also 4H‐SiC and Al 2 O 3 have large conduction band offset so Al 2 O 3 has been preferred over SiO 2 as a gate dielectric 16–21 . The device performance can furthermore be enhanced by incorporating gate‐stack HfO 2 along with Al 2 O 3.…”

“…15 Al 2 O 3 has excellent lattice match with SiC, high thermal stability, superior compatibility with 4H-SiC, also 4H-SiC and Al 2 O 3 have large conduction band offset so Al 2 O 3 has been preferred over SiO 2 as a gate dielectric. [16][17][18][19][20][21] The device performance can furthermore be enhanced by incorporating gate-stack HfO 2 along with Al 2 O 3. Gate-stack HfO 2 has high dielectric constant and kinetic energy.…”

Influence of Atomic Layer Deposition Temperature on the Electrical Properties of Al/ZrO2/SiO2/4H‐SiC Metal‐Oxide Semiconductor Structures

“…It is also known that deposition conditions like process temperature can affect the properties of dielectric thin films such as crystal or amorphous structure and alters gate stack properties . While there were several works on the properties of double gate dielectric stacks prepared using atomic layer deposition of high‐κ dielectrics like HfO 2 /SiO 2 , La 2 O 3 /SiO 2 , Al 2 O 3 /SiO 2 , Al 2 O 3 /SiO x N y , or Pr x O y /AlON on 4H‐SiC, there is no information about ZrO 2 /SiO 2 gate stacks and the influence of the deposition temperature on the electrical properties of double dielectrics stacks on 4H‐SiC although deposition temperature has significant influence on both structural and electrical properties of various ALD fabricated high‐κ dielectrics . In this work, we investigate the effect of deposition temperature on the electrical properties of atomic layer deposited (ALD) ZrO 2 /thermally oxidized SiO 2 gate stacks on 4H‐SiC.…”

Electronic Properties of Stacked ZrO2 Films Fabricated by Atomic Layer Deposition on 4H-SiC

“…Although SiC can be thermally oxidized resulting in formation of SiO 2 layer, the application of relatively small dielectric constant material (κ SiO2 = 3.9) leads to a premature breakdown of the MOSFET gate. Since the breakdown mechanism of the device is related to the Gauss law the high-κ dielectrics were proposed as an alternative gate material for SiC power devices [2][3][4]. Hafnium oxide (HfO 2 ) [2], aluminum oxide (Al 2 O 3 ) [3] or zirconium oxide (ZrO 2 ) [4] single dielectric layers have been investigated in recent years for application as gate dielectric.…”

“…Since the breakdown mechanism of the device is related to the Gauss law the high-κ dielectrics were proposed as an alternative gate material for SiC power devices [2][3][4]. Hafnium oxide (HfO 2 ) [2], aluminum oxide (Al 2 O 3 ) [3] or zirconium oxide (ZrO 2 ) [4] single dielectric layers have been investigated in recent years for application as gate dielectric. However, two main drawbacks limit a successful implementation: HfO 2 and ZrO 2 , materials with dielectric constant higher than that for SiC (κ SiC = 9.66), have been reported to form relatively small conduction band offset for electrons resulting in an extensive leakage current (≈ 1.07 eV for HfO 2 and ≈ 0.94 eV for ZrO 2 , respectively [5]).…”