Characterization of a Fault-tolerant NoC Router

Abstract

Abstract-With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore architectures. Another concern for these architectures is increasing global wire lengths with associated issues leading to network-on-chips (NoC) becoming standard for on-chip global communication. We recognize these issues and present an onchip generic fault-tolerant routing algorithm. The microarchitecture of a NoC router implementing the proposed routing algorithm for a k-ary 2-cube topology is provided. The proposed router works in two phases. In the first phase, the network is explored for an existing path between sourcedestination pairs after reset or during system reconfiguration after fault detection. Existing paths are cached and used in the second phase of data communication during normal system operation. The presented router architecture also proposes a concept of dynamic multiplexing of virtual channels on physical channels to efficiently utilize physical channel bandwidth. The above approaches complement each other and when combined together, result in an efficiently realizable high-performance NoC fault-tolerant router. An implementation characterization of this k-ary 2-cube torus router in terms of area, power and critical path delay in IBM Cu-08 technology is presented, along with bandwidth and latency characterization for relevant cases.

Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router

“…The router works as follows in the first path exploration (PE) phase [3] [4] with the objective of finding existing simple paths between all pair of nodes: -1. At the source node, send PE packet to all output ports ( Fig.…”

“…The default value of router parameters used are flit size equal to phit size of 512 bits (L1 cache line size of Itanium 2 processor [5]), 4 VC [3], deadlock detection timer value of 256 cycles ( [6] suggests it to be good number for avoiding false deadlock detection), and deadlock buffer size of 1024 entries (sufficient for explored network sizes). Network size is currently limited to 49 nodes due to Cadence VHDL simulation environment constraints.…”

“…Network size is currently limited to 49 nodes due to Cadence VHDL simulation environment constraints. Simulation was run for 100µs, with a router cycle time [3] of 3ns. Validating the VHDL simulation framework was challenging given the highly detailed hardware simulation.…”

“…As a shared resource, bus-based architectures exhibit poor performance and fault-tolerance, and have inherent scaling limitations due to physical implementation issues. Consequently, NoC is becoming a standard for onchip global communication [2] [3].…”

“…Please refer [3] for their limitations. In contrast to previously proposed approaches, the proposed parallel (not sequential backtracking) and distributed (not centralized) routing algorithm [3] [4] finds a path if it exists between a pair of nodes beforehand and removes indeterminism from the completion of communication. Path exploration remains oblivious to injection rates and message lengths during normal system operation [3].…”