Characterization and Modeling of Temperature Effects in 3-D NAND Flash Arrays—Part II: Random Telegraph Noise

Nicosia, Gianluca; Mannara, Aurelio; Resnati, Davide; Paolucci, Giovanni M.; Tessariol, P.; Spinelli, A.S.; Lacaita, A.L.; Goda, Akira; Compagnoni, Christian Monzio

doi:10.1109/ted.2018.2839904

Cited by 28 publications

(11 citation statements)

References 27 publications

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“…This strengthening, which was not observed on planar cells [Fig. 10(a)], has been attributed to more relevant constraints set by polysilicon grain boundaries on channel conduction at lower temperatures, making conduction more percolative [64]. In addition, a much weaker dependence of RTN on the number of program/erase cycles performed on the cells has been reported [65].…”

Section: A Magnitude Of the Most Relevant Issues For Array Reliabilitymentioning

confidence: 89%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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Section: A Magnitude Of the Most Relevant Issues For Array Reliabilitymentioning

confidence: 89%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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“…The above-mentioned numerical models of conduction have been used to investigate the effect of GBs on variability in nanowires [ 90 , 91 , 92 , 93 , 94 , 95 ] and 3D NAND devices [ 96 , 97 ]. A recent study based on a drift-diffusion transport within the grains and thermionic emission at the GBs [ 98 , 99 , 100 , 101 ] has demonstrated a good capability to reproduce several features of experimental data, including its temperature dependence. Figure 3 (left) shows a typical conduction-band profile along the channel of a 3D NAND string, for increasing values of the control-gate bias, as resulting from such model.…”

Section: Polysilicon Conductionmentioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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“…Ideally case, a uniform program V th distribution between V PV (program-verify) and V PV + V Step can be obtained by ISPP algorithm [21]. Especially, program V th distribution can be distorted by ISPP noise [19], [20], WL-WL interference [22], and RTN effect of tunneling oxide and Poly-Si [23], [24], thus, the electron numbers in the nitride layer for a page memory cells are variable. Figure 4 shows the simulated single cell V th shift with different initial V th 4.5V, 4.7V, and 5.0V, respectively, where a self-consistent simulator (takes into consideration the tunneling processes, charge trapping/de-trapping mechanisms, and drift-diffusion transport within the storage layer) is used to simulate the program, erase, retention, and read operations as calibrated and verified in our previous works [25]- [27].…”

Section: Retention Characteristicsmentioning

confidence: 99%

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Wang

Lun³

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention V th distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated V th distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the V th distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory. INDEX TERMS Retention V th distribution, retention noise, 3-D TLC NAND flash memory, reliability.

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Characterization and Modeling of Temperature Effects in 3-D NAND Flash Arrays—Part II: Random Telegraph Noise

Cited by 28 publications

References 27 publications

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Random Telegraph Noise in 3D NAND Flash Memories

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

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