Chaos computing for mitigating side channel attack

Majumder, Md. Badruddoja; Hasan, Sakib; Uddin, Mesbah; Rose, Garrett S.

doi:10.1109/hst.2018.8383903

Cited by 22 publications

(6 citation statements)

References 12 publications

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“…Additionally, some types of cryptography were believed to be resistant to SCA by their nature. For example, chaos cryptography [ 82 , 83 ] was expected to be hard to attack because of its unpredictable behaviour [ 84 ]. Nevertheless, these beliefs were disproven, e.g., by a study showing that the chaos-based S-Boxes are similarly vulnerable to SCA as the AES ones [ 85 ].…”

Section: Countermeasures Against Attacksmentioning

confidence: 99%

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

Socha

Miškovský²,

Novotný³

2022

Sensors

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Side-channel analysis has become a widely recognized threat to the security of cryptographic implementations. Different side-channel attacks, as well as countermeasures, have been proposed in the literature. Such attacks pose a severe threat to both hardware and software cryptographic implementations, especially in the IoT environment where the attacker may easily gain physical access to a device, leaving it vulnerable to tampering. In this paper, we provide a comprehensive survey regarding the non-invasive passive side-channel analysis. We describe both non-profiled and profiled attacks, related security metrics, countermeasures against such attacks, and leakage-assessment methodologies, as available in the literature of more than twenty years of research.

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Section: Countermeasures Against Attacksmentioning

confidence: 99%

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

Socha

Miškovský²,

Novotný³

2022

Sensors

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“…For obfuscation applications, it is highly desirable to have a large functionality space so that multiple reliable configurations can be chosen for implementing a single function. This can be leveraged to ensure the security of chaosbased computing systems against side-channel power analysis based attacks [7], [14]. Previously, this was achieved using many iterations but this poses a problem since the resulting gate becomes increasingly unreliable.…”

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

“…This approach can significantly reduce the overhead for implementing complex logic functions. Moreover, as shown in [14], oftentimes we only have to replace a small percentage of total gates with chaos-based implementation to benefit from the resulting security advantages.…”

Section: Enhancement Of the Functionality Spacementioning

confidence: 99%

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Hasan

Shanta

Paul

et al. 2020

2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)

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In this paper, a novel chaotic map is introduced using a voltage controlled negative differential resistance (NDR) circuit composed of an n-channel and a p-channel silicon-on-insulator (SOI) four-gate transistor (G 4 FET). The multiple gates of the G 4 FET are leveraged to create a discrete chaotic map with three bifurcation parameters. The three tunable parameters are the gain of a transimpedance amplifier (TIA), top-gate voltage of nchannel G 4 FET, and top-gate voltage of p-channel G 4 FET. Two methods are proposed for building chaotic oscillators using this discrete map. The effect of altering bifurcation parameters on chaotic operation is illustrated using bifurcation diagrams and Lyapunov exponent. A design methodology for building flexible and reconfigurable logic gate is outlined and the consequent enhancement in functionality space caused by the existence of three independent bifurcation parameters is demonstrated and compared with previous work.

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“…G 4 FET inspired multiple state electrostatically formed nanowires have already been used for threshold logic functions [6] and high-sensitivity gas sensing [7]. Another potential application is to leverage the tunable tent map shape characteristics of the voltage controlled G 4 NDR circuit [2] to build chaotic logic gates for hardware security applications [8,9].…”

Section: Silicon-on-insulator (Soi) Four Gate Field Effect Transistormentioning

confidence: 99%

Modeling Emerging Semiconductor Devices for Circuit Simulation

Hasan¹,

Shawkat²,

Amer³

et al. 2020

Computational Models in Engineering

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Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore's Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicon-oninsulator four gate transistor(G 4 FET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.

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Chaos computing for mitigating side channel attack

Cited by 22 publications

References 12 publications

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map

Modeling Emerging Semiconductor Devices for Circuit Simulation

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Chaos computing for mitigating side channel attack

Cited by 22 publications

References 12 publications

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

A Comprehensive Survey on the Non-Invasive Passive Side-Channel Analysis

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map

Modeling Emerging Semiconductor Devices for Circuit Simulation

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Resources

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Design of an Enhanced Reconfigurable Chaotic Oscillator using G⁴FET-NDR Based Discrete Map