Channeled MeV B, P and As Profiles in Si(100): Monte-Carlo Models and SIMS

Current, Michael; Kawasaki, Yoji; Hobler, G.; Sugitani, M.

doi:10.1109/iit.2018.8807901

Cited by 3 publications

(4 citation statements)

References 8 publications

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“…Details of implant conditions and characterization results, including secondary ion mass spectroscopy (SIMS) depth profiles with implant channeling simulation results can be found elsewhere. 8,9 Boron SIMS depth profile showed double B concentration peaks of ∼1.2 × 10 17 cm −3 at 2.4 μm and 3.0 μm from the surface. A double peaked Boron profile is the results of a highly-channeled ion beam orientation.…”

Section: Methodsmentioning

confidence: 97%

“…The deeper peak are made up of channeled ions that and the shallower peak is corresponding to scattered ions with "random" incidence paths (as was confirmed by Monte Carlo modeling). 8,9 Room temperature PL.-To investigate the effect of 11 B + implant temperature, PL spectra (PL intensity and spectral distribution in the wavelength range of 900-1400 nm) were measured under 670 nm and 827 nm excitation. A fully automated, specially designed spectrograph capable of measuring 300 mm diameter wafers, with a thermoelectrically cooled InGaAs linear diode array (WaferMasters MPL-300) was used for room temperature PL measurements.…”

Section: Methodsmentioning

confidence: 99%

“…[1][2][3][5][6][7] This can be considered as an extended application of an MeV ion implantation technique developed for formation of deep junctions and image sensor devices. 8,9 Non-contact, non-destructive in-line monitoring of metal impurity contaminants, defects, interface states and any unexpected irregularities and non-uniformities becomes very important from the industrial point of view. Electronic and optical properties of Si have been studied by photoluminescence spectroscopy for decades.…”

mentioning

confidence: 99%

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Effects of Implant Temperature, Backside Contamination and Scribe Lines on Room Temperature Photoluminescence Measurements on Silicon

Yoo

Ishigaki

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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To investigate the effect of implantation temperature on the damage to a Si lattice, room temperature photoluminescence (PL) spectra were measured from highly-channeled MeV 11B+ implanted Si wafers with different implant temperatures (25 °C and 450 °C) after annealing at 950 °C for 3 min in N2. Small pieces from the wafers were used for PL characterization. The implanted Si wafer piece at the elevated temperature resulted in higher overall PL intensity under both excitation wavelengths suggesting lesser lattice damage than the Si wafer implanted at room temperature. Unexpectedly large PL intensity variations were observed from PL area mapping of both wafer pieces. In addition, strange behaviors of localized PL intensity variations, with opposite trends between 670 nm and 827 nm excitation PL measurements were observed near the scribe lines and sample number markings on the backside. The PL intensity was increased under 670 nm excitation while it was decreased under 827 nm excitation. Possible reasons for this strange behavior were discussed based on experimental results and analysis. PL measurement is verified to be very sensitive to the surface condition, interface, bulk and backside conditions of the Si. For reliable PL measurement, backside contamination and scratches, such as scribe lines, should be avoided.

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Section: Methodsmentioning

confidence: 97%

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Effects of Implant Temperature, Backside Contamination and Scribe Lines on Room Temperature Photoluminescence Measurements on Silicon

Yoo

Ishigaki

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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“…Despite the fact that channeling has been studied since the early 60s [1][2][3][4][5][6][7], an adequate analytical model of ion channeling in the low-energy region is still not built and continues to be the subject of theoretical and experimental work.…”

Section: Introductionmentioning

confidence: 99%

Manifestation of the channeling effect when manufacturing JFET transistors

Verbitskiy¹,

Voevodin²,

Fedulov³

et al. 2020

SPQEO

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TThe proposed work covers the tasks of such areas as reducing input currents and bias voltage of integrated operational amplifiers (ICs OA) manufactured according to BiFET technology, the prospect of using JFET transistors in digital circuit technology, Si CMOS technology at 22 nm node and beyond, manufacturing bipolar transistors on ultra-thin layers of the active base and emitter, increasing resistance of ICs to external influences. The main method of experimental investigation of channeling is the construction of impurity distribution profiles using SIMS. In this work to study the channeling effect of boron and phosphorus in silicon was chosen the method for constructing the response surface of the saturation current of JFET for a silicon wafer. The choice of method was based on the high sensitivity of the cut-off voltage and saturation current of the JFET transistor to the channel thickness and impurity concentration in it, the relative simplicity of performance and practical benefits in improving BiFET technology.

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