Channel hot carrier induced volatile oxide traps responsible for random telegraph signals in submicron pMOSFETs

Rouf, A. S. M. Shamsur; Çelik‐Butler, Zeynep

doi:10.1016/j.sse.2019.107745

Cited by 9 publications

(4 citation statements)

References 40 publications

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“…Sensors 2023, 23, x FOR PEER REVIEW 2 of 14 in the literature [30][31][32][33][34], the statistical characterization involving a large sample size was not reported before. In this work, we study the effects of HCI stress on RTN and the threshold voltage shift of NMOS in an 8.3Mpixel CIS.…”

Section: Test Chip Architecture and Characteristicsmentioning

confidence: 99%

“…On the other hand, the hot carrier injection (HCI), together with the time dependent dielectric breakdown (TDDB), the bias temperature instability (BTI), and the electron migration (EM), are the most important aging and reliability issues for advanced CMOS devices [ 23 , 24 , 25 , 26 , 27 , 28 , 29 ]. Although the RTN degradation of MOS transistors due to HCI was known in the literature [ 30 , 31 , 32 , 33 , 34 ], the statistical characterization involving a large sample size was not reported before. In this work, we study the effects of HCI stress on RTN and the threshold voltage shift of NMOS in an 8.3Mpixel CIS.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Random Telegraph Noise Degradation Caused by Hot Carrier Injection in a 0.8 μm-Pitch 8.3Mpixel Stacked CMOS Image Sensor

Chao,

Wu,

Yeh

et al. 2023

Sensors

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In this work, the degradation of the random telegraph noise (RTN) and the threshold voltage (Vt) shift of an 8.3Mpixel stacked CMOS image sensor (CIS) under hot carrier injection (HCI) stress are investigated. We report for the first time the significant statistical differences between these two device aging phenomena. The Vt shift is relatively uniform among all the devices and gradually evolves over time. By contrast, the RTN degradation is evidently abrupt and random in nature and only happens to a small percentage of devices. The generation of new RTN traps by HCI during times of stress is demonstrated both statistically and on the individual device level. An improved method is developed to identify RTN devices with degenerate amplitude histograms.

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Section: Test Chip Architecture and Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Random Telegraph Noise Degradation Caused by Hot Carrier Injection in a 0.8 μm-Pitch 8.3Mpixel Stacked CMOS Image Sensor

Chao,

Wu,

Yeh

et al. 2023

Sensors

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“…The influence of a single trapped charge on the noise characteristics has been widely investigated for the planar MOSFETs [9][10][11][12] and FinFETs [13,14], while very few works were devoted to investigating the RTN amplitude in the relatively new Junctionless FinFET [15,16]. Thus, the influence of both shape and size of the single trapped charge to noise characteristics of nanometer Junctionless FinFET is closely studied in this paper.…”

Section: Introductionmentioning

confidence: 99%

Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET

et al. 2020

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In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects with different sizes and shapes on the amplitude of the random telegraph noise (RTN) in Junctionless Fin Field Effect Transistor (FinFET) is modelled and simulated. The RTN amplitude dependence on the number of single charges trapped in a single defect is modelled and simulated too. It is found out that the RTN amplitude in the Junctionless FinFET does not depend on the shape, nor on the size of the single defect area. However, the RTN amplitude in the subthreshold region does considerably depend on the number of single charges trapped in the defect.

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“…That is, the frequency exponent γ after HCS 10k decreased from 1.34 to 1.06, which indicates an increase in N it that react rapidly the interface traps close to the channel region while an increase of the γ over 1 value means an increase in the number of border traps (N t ) that react slowly the deep traps within the gate oxide region. [22][23][24] Unlike the channel-HCS in a MOSFET, [25][26][27] the fast reaction via the generation of interface traps from channel/gate oxide region near the source tunneling junction in TFET after HCS cause weak impacts on the drain current, and the generated active traps exist in the tunnel junction of TFET.…”

mentioning

confidence: 99%

Correlation between low-frequency noise and interface traps of fully-depleted silicon-on-insulator tunneling FETs induced by hot carrier stress

Shin¹,

Song²,

Song³

et al. 2020

Jpn. J. Appl. Phys.

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The generation of interface traps at the drain corner during hot-carrier-stress (HCS) in a fully-depleted silicon-on-insulator tunneling field-effect transistor (TFET) was invested and correlated to low-frequency noise performance. The hot carrier damage increases the number of the generated interface traps because hot carriers could gain high kinetic energy to reach the conduction band near the drain region in TFET. Unlike the results of channel-HCS characteristics in MOSFETs, the frequency exponent γ under the same stress voltage conditions in TFET decreased by 21.4%, which was attributed by the generation of interface traps as compared to deeper border traps.

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Channel hot carrier induced volatile oxide traps responsible for random telegraph signals in submicron pMOSFETs

Cited by 9 publications

References 40 publications

Random Telegraph Noise Degradation Caused by Hot Carrier Injection in a 0.8 μm-Pitch 8.3Mpixel Stacked CMOS Image Sensor

Random Telegraph Noise Degradation Caused by Hot Carrier Injection in a 0.8 μm-Pitch 8.3Mpixel Stacked CMOS Image Sensor

Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET

Correlation between low-frequency noise and interface traps of fully-depleted silicon-on-insulator tunneling FETs induced by hot carrier stress

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