Channel Engineered Cylindrical Double Gate All Around FET For Low Power VLSI Applications

Quader, Sakib; Siddik, Abu Bakar; Hossain, Nazir; Chowdhury, Md. Iqbal Bahar

doi:10.1109/ic4me2.2018.8465589

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2020

2021

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“…Many alternative structures like Double gate MOSFET [5][6][7], Triple gate MOSFET [8], Tunnel FET [9], Gate all around FET's [10] are proposed for reducing SCE's. FinFET comes under the classification of a triple gate device.…”

Section: Introductionmentioning

confidence: 99%

Design, Simulation and Analysis of Junction Version Multi-Fin FINFET

Rao

Vandana

2021

Silicon

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This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (µ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

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