Changing interaction of compiler and architecture

Adve, Sarita V.; Burger, Douglas C.; Eigenmann, Rudolf; Rawsthorne, Alasdair; Smith, Michael D.; Gebotys, Catherine H.; Kandemir, Mahmut; Lilja, David J.; Choudbary, A.N.; Fang, Juan; Yew, Pen-Chung

doi:10.1109/2.642815

Cited by 19 publications

(9 citation statements)

References 16 publications

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“…This is supported by retargetable and memory optimizing compilers [5,6,7,8]. The trade-off is here between fine-grain software control (instruction control overhead) and associated data access bottleneck (overhead from register-register operation), and accelerators implementing complex operations.…”

Section: Related Workmentioning

confidence: 99%

Flexible hardware acceleration for multimedia oriented microprocessors

Vermeulen

Nachtergaele

Catthoor

et al. 2000

Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture

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The execution of multimedia applications on a microprocessor greatly benefits from hardware acceleration, both in terms of speed and energy consumption. While the basic functionality implemented in these accelerators remains constant over different product versions, small changes are still often required. With the proposed architecture and protocol, the accelerator hardware has the performance and cost benefits of a hardwired solution, while featuring all the flexibility needed in practice. From a user point of view, the entire application is still programmable.

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Section: Related Workmentioning

confidence: 99%

Flexible hardware acceleration for multimedia oriented microprocessors

Vermeulen

Nachtergaele

Catthoor

et al. 2000

Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture

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“…Classic code optimizations such as function inlining, dead code elimination, and loop invariant removal become more effective with profiling [6]. Dynamic code optimization frameworks incorporate monitoring and analysis of program behavior seamlessly with code optimizations at run time [1,2,22].…”

Section: Related Workmentioning

confidence: 99%

“…Most system resources in current platforms are considered homogeneous, making their management relatively simple. However, future multicore systems present significantly more asymmetry as: (1) Designers adopt asymmetry to achieve better performance, power and scalability, e.g., single-ISA heterogeneous chip multiprocessors [20], nonuniform cache architecture (NUCA) [17], switched onchip networks [3]; (2) Process variations render processor cores unintentionally asymmetric in terms of their performance and power consumption [4]; (3) Imperfect resource management strategies result in unbalanced and unfair resource usages, e.g., cache contention, thermal emergencies; and (4) Growing fragility in process technology will give rise to intermittent and permanent faults while a system is operational [30]. The difficulty of tackling significant asymmetry in system resources will only grow as the amount of such resources increases.…”

Section: Introductionmentioning

confidence: 99%

MAESTRO: Orchestrating predictive resource management in future multicore systems

Cho

Demetriades

2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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In this position paper, we make a case for a novel framework called MAESTRO which predictively manages system resources in shared-memory parallel computing platforms built with advanced multicore processors. In such platforms, effectively coordinating the use of asymmetric shared system resources under complex program execution scenarios becomes hard. Current resource management strategies are mostly reactive and have limited awareness of an application's resource usage and asymmetry in hardware resources. For better resource management, MAESTRO monitors the program execution environment (hardware/OS) and application behaviors, learns useful knowledge from collected information, annotates the results of the learning to relevant program and system control structures, and makes resource management decisions such as task mapping and cache partitioning in a predictive manner.978-1-4577-0599-1/11/$26.00 ©2011 IEEE

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“…Many techniques have been proposed to reduce energy consumption in different aspects of the ICMH [6]. Several bus encoding schemes [7,8] have been applied to reduce the effective switching on the (instruction and address) buses.…”

Section: Related Workmentioning

confidence: 99%

Design Style Case Study for Embedded Multi Media Compute Nodes

Lambrechts

Jayapala

et al.

25th IEEE International Real-Time Systems Symposium

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Context and motivationThe merging of mobile phones, electronic agendas, multimedia computers and (broadband) communication networks gives rise to very fast growing markets for handheld communication and entertainment devices. Technology advances lead to platforms with enormous processing capacity. However, for handheld terminals the energy consumption is currently the limiting factor. At the same time, achieving real-time performance for the processing kernels is still a challenge. Major innovative solutions are needed to merge energy efficiency and high performance into a single embedded processor. A first step in this direction is the evolution from RISC to VLIW. VLIW processors provide more computing resources, and rely heavily on the compiler to figure out how to use these resources efficiently. This means that energy inefficient hardware resources (e.g. dispatch unit) that are extensively used in super scalar processors can be avoided. Because even higher performance and higher energy efficiency is needed, different, mostly domain specific, VLIW-descendants are currently being developed. However, no clear overview of these different design styles and their advantages and disadvantages, was available up to now in public literature. To be fair and really valid this overview needs to be based on concrete data for the same realistic application, that was separately optimised for the different styles.Because different processors tend to be more optimal for different applications or modes of operation, most of the emerging SoC platforms are heterogeneous in nature. They contain several types of compute nodes and memory nodes. This work fits into a bigger research activity that estimates the energy consumption of all parts of such a platform. The energy consumption of this global platform can be considered to consist of three main parts: the data-path logic of the compute nodes (computational circuits, combined with local register files that are usually quite dominant), the data memory hierarchy (from level 1 upwards) and the instruction/configuration memory hierarchy (which we will abreviate ICMH in the rest of the paper.In this paper, we will present the data obtained from our case study covering different design options for the

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Changing interaction of compiler and architecture

Cited by 19 publications

References 16 publications

Flexible hardware acceleration for multimedia oriented microprocessors

Flexible hardware acceleration for multimedia oriented microprocessors

MAESTRO: Orchestrating predictive resource management in future multicore systems

Design Style Case Study for Embedded Multi Media Compute Nodes

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