Design Style Case Study for Embedded Multi Media Compute Nodes

Abstract

Context and motivationThe merging of mobile phones, electronic agendas, multimedia computers and (broadband) communication networks gives rise to very fast growing markets for handheld communication and entertainment devices. Technology advances lead to platforms with enormous processing capacity. However, for handheld terminals the energy consumption is currently the limiting factor. At the same time, achieving real-time performance for the processing kernels is still a challenge. Major innovative solutions are needed to merge energy efficiency and high performance into a single embedded processor. A first step in this direction is the evolution from RISC to VLIW. VLIW processors provide more computing resources, and rely heavily on the compiler to figure out how to use these resources efficiently. This means that energy inefficient hardware resources (e.g. dispatch unit) that are extensively used in super scalar processors can be avoided. Because even higher performance and higher energy efficiency is needed, different, mostly domain specific, VLIW-descendants are currently being developed. However, no clear overview of these different design styles and their advantages and disadvantages, was available up to now in public literature. To be fair and really valid this overview needs to be based on concrete data for the same realistic application, that was separately optimised for the different styles.Because different processors tend to be more optimal for different applications or modes of operation, most of the emerging SoC platforms are heterogeneous in nature. They contain several types of compute nodes and memory nodes. This work fits into a bigger research activity that estimates the energy consumption of all parts of such a platform. The energy consumption of this global platform can be considered to consist of three main parts: the data-path logic of the compute nodes (computational circuits, combined with local register files that are usually quite dominant), the data memory hierarchy (from level 1 upwards) and the instruction/configuration memory hierarchy (which we will abreviate ICMH in the rest of the paper.In this paper, we will present the data obtained from our case study covering different design options for the

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors

“…Figure 4 shows an example of two schedules, corresponding two possible schedules and two possible L0 clusters, and its estimated energy for a 12-slots VLIW processor; such large number of slots are beneficial for multimedia and wireless applications that exhibit large ILP [Gangwar et al 2005;Lambrechts et al 2004]. MIMO (multiple-input multiple-output) wireless application is a good example to exploit high ILP [Scarpazza et al 2006].…”