Challenges of Ultra-Thin 5 Sides Molded WLCSP

Tang, Tom; Lan, Albert; Wu, Jason; Huang, Joe; Tsai, Jensen; Li, Jerry; Ho, Arthur; Chang, Jae Joon; Lin, Wh

doi:10.1109/ectc.2016.51

Cited by 19 publications

(2 citation statements)

References 3 publications

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“…After curing of the epoxy mold compound (EMC), grinding of the wafer backside is performed to achieve the package thickness. Challenges of the molded WLCSPs came from back-grinding and the wafer warpage (Tang et al, 2016). Kuo et al (2016) investigated the reliability of fan-in WLPs and the effect of post-wafer grinding.…”

Section: Polishing and Grinding For Fan-out Wafer Level Packagesmentioning

confidence: 99%

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Recent advances and applications of abrasive processes for microelectronics fabrications

Zhong

2019

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Purpose This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications. Design/methodology/approach More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs). Findings Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding. Originality/value This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

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Section: Polishing and Grinding For Fan-out Wafer Level Packagesmentioning

confidence: 99%

“…This is because microelectronics packages have to be miniaturized, due to the continuous demand for light and thin mobile devices. Challenges come from back-grinding and the wafer warpage (Tang et al, 2016).…”

Section: Introductionmentioning

confidence: 99%