Challenges in Future-Generation Interconnects: Microstructure Again

Abstract

The aim of this chapter is not to introduce the packaging technology of the future nor the challenges in specific packaging structure. Rather, it is to review the characteristics of technology on the horizon along with the introduction of materials under consideration, briefly consider possible problems associated with such technology, and stress the need for understanding more on the solder itself. For this, this chapter firstly discusses the need for considering new boundary condition of the interconnects that arise from the use of electronics in harsher environment in a small form factor. It is followed by the discussion on the packaging challenges in higher power devices such as the power handling devices and LEDs. Then, material challenges associated with device miniaturization as well as the increased current density in solder interconnects are presented. Finally, the need for and difficulty in developing multiscale model for solder joint property and its behaviors in packaging structure is briefly discussed in order to reemphasize the urgency of achieving more advanced understanding of the Pb-free solder materials in general. Future Packaging and Next-Generation Interconnects: KeywordsThe keywords for future packaging and next-generation interconnects are smaller form factor, higher performance, flexible in form factor and applications, and lower power consumption than the devices used in today's technology. Demand for such devices emerges as electronic devices are increasingly used in unconventional places, and this trend will only increase in the foreseeable future. Such devices will be designed with miniaturization, wider applications, extreme environments, wearable electronics, low power, flexible, more functionality, vertical stacking and 3D architectures, active thermal management, and high current density as design goals and constraints. Critical issues in relation to the development of such devices include the power device package design, MEMS, 3D wafer-level packages, complex

Selective etching and hardness properties of quenched SAC305 solder joints

“…This made them less detectable during XRD analysis (lower intensities). The appearance of the a-Sn phase in the case of ice-quenched cooling was because of the allotropic transition of b -Sn below 13.2°C (Lee et al, 2015). Previous results clearly showed the influence of the cooling condition on the formation of the different phases in the SAC305 solder joints.…”