Challenges for large-scale implementations of spiking neural networks on FPGAs

Maguire, Liam; McGinnity, T.M.; Glackin, Brendan; Ghani, Arfan; Belatreche, Ammar; Harkin, Jim

doi:10.1016/j.neucom.2006.11.029

Cited by 163 publications

(98 citation statements)

References 37 publications

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“…Rotation and Phase Counter RR [0] MNT [0] RR [1] MNT [1] RR [2] MNT [2] RR [3] MNT [3] RR [4] MNT [4] RR [5] MNT [5] RR [6] MNT [6] RR [7] MNT [7] Generated spike packets are processed and forwarded in a single clock cycle. Full rotation of the spike packet on the ring ensures broadcast packet flow control.…”

Section: Fixed Latency Spike Flow-controlmentioning

confidence: 99%

“…The efficient implementation of hardware SNN architectures for real-time embedded systems is primarily influenced by neuron design, scalable on-chip interconnect architecture and SNN training/learning algorithms [7]. Packet switched Network on Chip (NoC) architectures have recently been proposed as the spike communication infrastructure for hardware SNNs, where data packets containing spike information are routed over a network of routers.…”

Section: Introductionmentioning

confidence: 99%

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Fixed latency on-chip interconnect for hardware spiking neural network architectures

Pande¹,

Morgan²,

Smit³

et al. 2013

Parallel Computing

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Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter alters spike timings and distorts the information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour. This paper presents a simulation-based analysis of this synaptic information distortion in NoC based hardware SNNs.The paper proposes a ring topology interconnect for spike communication between neural tiles, and a timestamped spike broadcast flow control scheme that offers fixed spike transfer latency. The proposed architectural technique is evaluated using spike rates employed in previously reported hardware SNN applications. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion.The paper presents the micro-architecture of the proposed ring router. The ring interconnect architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Limitations on the scalability of the proposed ring architecture and selection of the optimal ring size based on spike rate resolution and hardware resources are discussed. A hierarchical, mesh topology NoC architecture with a 4 × 8 modular neural elements supporting 896 neurons and 72K synapses on a Xilinx Virtex-6 XC6VLX240T FPGA device is presented.

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Section: Fixed Latency Spike Flow-controlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fixed latency on-chip interconnect for hardware spiking neural network architectures

Pande¹,

Morgan²,

Smit³

et al. 2013

Parallel Computing

View full text Add to dashboard Cite

show abstract

“…Maass has demonstrated that spiking neurons are more computationally powerful than threshold-based neuron models [24] and that SNNs possess similar and often more computation ability compared to second generation multi-layer perceptrons [25]. Other works [26][27][28] have investigated SNN hardware implementations and have found that computation in the temporal domain can be performed more efficiently in hardware compared to employing complex non-linear sigmoidal neural models. These findings, and an increasing interest in efficient temporal computation have encouraged interest in SNNs and their application to classification and control tasks.…”

Section: Spiking Neural Networkmentioning

confidence: 99%

Spiking Neural Networks for Breast Cancer Classification in a Dielectrically Heterogeneous Breast

O’Halloran¹,

McGinley²,

Conceição³

et al. 2011

PIER

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Abstract-The considerable overlap in the dielectric properties of benign and malignant tissue at microwave frequencies means that breast tumour classification using traditional UWB Radar imaging algorithms could be very problematic. Several studies have examined the possibility of using the Radar Target Signature (RTS) of a tumour to classify the tumour as either benign or malignant, since the RTS has been shown to be influenced by the size, shape and surface texture of tumours. The main weakness of existing studies is that they mainly consider tumours in a 3D dielectrically homogenous or 2D heterogeneous breast model. In this paper, the effects of dielectric heterogeneity on a novel Spiking Neural Network (SNN) classifier are examined in terms of both sensitivity and specificity, using a 3D dielectrically heterogeneous breast model. The performance of the SNN classifier is compared to an existing LDA classifier. The effect of combining conflicting classification readings in a multi-antenna system is also considered. Finally and importantly, misclassified tumours are analysed and suggestions for future work are discussed.

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“…In reconfigurable architectures, the model can modify the hardware configuration of the chip while the simulation is running. Either through component swapping [12] or network remapping [56], these approaches seek to circumvent scalability limitations, with some success, but with both FPGA's and GPU's scalability has proven to be the main problem, with FPGA's running into routing barriers due to their circuit-switched fabric [33] and GPU's running into memory access barriers. Even more problematic has been power consumption: a typical large FPGA may dissipate ∼ 50W and a GPU accelerator ∼ 200W.…”

Section: Adapted General-purpose Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

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Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

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Challenges for large-scale implementations of spiking neural networks on FPGAs

Cited by 163 publications

References 37 publications

Fixed latency on-chip interconnect for hardware spiking neural network architectures

Fixed latency on-chip interconnect for hardware spiking neural network architectures

Spiking Neural Networks for Breast Cancer Classification in a Dielectrically Heterogeneous Breast

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

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