Challenges for Future Semiconductor Manufacturing

Abstract

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

“…According to the ITRS prediction, the feature size or physical channel length of MOS devices will soon enter the sub 10-nm range. There would be needed tremendous efforts to achieve this goal as we are pushing both the technological capability and material properties to their ultimate limits [5][6][7][8][9][10][11][12][13].…”

Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

“…A fundamental property of the PC method is that the basis functions must satisfy the orthogonality relation (4). In general, the inner product in (4) can be defined for different types of weighting function W (ξ); however, it is possible to prove that the optimal convergence rate of a PC model can be achieved when the weighting function W (ξ) corresponds to the joint PDF of the random variables considered expressed in a standard form, since the random variables ξ are normalized [13,32].…”

“…In particular, the advances in manufacturing process technology is one of the core factors that make manufacturing ICs in the sub-micrometer region possible. However, various technological challenges emerge when such small geometries are used to realize large-scale ICs [4]. …”

Cost-Benefit Analysis of Computer-Aided Technology Customization Projects

“…With the advancement of mobile computing, social networking, smart-electronic products, and 5G initiatives, it has become mandatory for the IC manufacturers to offer high density products with multiple circuit functions, what is known today as "System-on-a-Chip (SoC)" [6]. The design and manufacturing of SoCs are extremely complex due to the increased complexities of IC devices and fabrication technology at nano nodes [7] [8] [9] [10] [11]. With the increased complexities of SoC design, it is no longer costeffective for fabless design companies to acquire and manage head counts and core competencies in-house.…”