Challenges and Solutions of the TFET Circuit Design

Lin, Zhiting; Chen, Panpan; Ye, Le; Xu, Yan; Dong, Lanzhi; Zhang, Shuguang; Zhou, Yang; Peng, Chunyu; Wu, Xiulong; Chen, Junning

doi:10.1109/tcsi.2020.3010803

Cited by 22 publications

(16 citation statements)

References 44 publications

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“…Recently, several works have explained about TFET p-i-n forward current and the phenomenon behind its occurrence. [31][32][33] Apart from this, in the fourth quadrant with V GS > 0 and V DS < 0, TFET works as tunnel diode and exhibits NDR characteristics. [31][32][33]37,38 This TFET model is popularly known as universal TFET model and explored by several researchers for the TFET circuit design.…”

Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

“…[31][32][33] Apart from this, in the fourth quadrant with V GS > 0 and V DS < 0, TFET works as tunnel diode and exhibits NDR characteristics. [31][32][33]37,38 This TFET model is popularly known as universal TFET model and explored by several researchers for the TFET circuit design. 37,38 In this work, TFET circuits have been implemented using Verilog-A netlist and simulated exploring industry standard Synopsys h-spice environment.…”

Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

“…Several works have explained the concept of TFET forward current and demonstrated it experimentally. [31][32][33] Table 1 compares the divergent TFET designs and the reported p-i-n forward current in the literature. It shows that TFET demonstrates significant forward current and it is relatively lower compared to ON current.…”

Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

“…31 Several techniques have been demonstrated to avoid this forward current for general circuit design. 32,33 Orthogonal to this, the p-i-n forward current of TFET is explored as favorable feature to enhance the hardware security of circuits/systems. [34][35][36] In the recent works, authors have proposed TFET p-i-n forward based TRNG design that shows higher resilience towards reverse engineering attacks.…”

Section: Introductionmentioning

confidence: 99%

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Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Japa

Majumder

Sahoo

et al. 2021

Circuit Theory & Apps

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Conventional complementary metal oxide semiconductor (CMOS)-based dedicated true random number generator (TRNG) and physically unclonable function (PUF) designs have exhibited higher energy consumption and large area overhead with technology scaling. In contrast, this paper for the first time presents emerging tunnel field-effect transistor (TFET)-based ultra-lightweight reconfigurable TRNG and PUF design. A unique methodology is proposed that considers p-i-n forward current characteristics to generate random keys for PUF and TRNG designs. Leveraging the p-i-n forward current of TFET, a ring oscillator (RO) is designed that exhibits variation in the operating frequency and acts as the main source of entropy for both PUF and TRNG. The TRNG in the proposed design is robust and passed all the National Institute of Standards and Technology (NIST) tests. Considering the variation in p-i-n forward current, the uniqueness of PUF is calculated as 47.5% and 46% at a supply voltage of 0.5 and 0.45 V, respectively. Moreover, PUF achieves high reliability of 82% and 88.7% with supply voltage and temperature variations, respectively. The proposed design is proved to be compact with relatively lower gate count and shows low energy consumption of 4.8 pJ/bit at 0.5-V supply voltage. With these performance metrics, the proposed design is highly suitable for resourceconstrained internet of things (IoT). K E Y W O R D Sinternet of things (IoT), physically unclonable function (PUF), p-i-n forward leakage, true random number generator (TRNG), tunnel field-effect transistor (TFET)

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Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

Section: Tfet Device Model and P-i-n Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Japa

Majumder

Sahoo

et al. 2021

Circuit Theory & Apps

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“…It can achieve a sub-threshold swing of less than 60mV/decade, enabling a further voltage scaling for higher energy efficiency without degrading the switching speed [9], [10]. It is reported that the power consumption can be reduced to less than 10% of a CMOS device with the same device size at the expense of at least 30% larger layout area and the complexity of layout design [11], [12]. However, TFET suffers from forward p-i-n current and gate dielectric reliability problem [12]- [14], which limits it from operating at a higher supply voltage.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices

Cai

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 µW, and ≤13,950 ns • nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99× improvement in PDP compared to the reported state-of-the-art LS architectures.Index Terms-Level shifter (LS), tunnel field-effect transistor (TFET), subthreshold circuit, ultra-low power, hybrid design, time-borrowing

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Operation Principle and Fabrication of TFET

Yirak,

Chaujar

2023

Advanced Ultra Low‐Power Semiconductor Devices

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Challenges and Solutions of the TFET Circuit Design

Cited by 22 publications

References 44 publications

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices

Operation Principle and Fabrication of TFET

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