Chainsaw: Von-neumann accelerators to leverage fused instruction chains

Sharifian, Amirali; Kumar, Snehasish; Guha, Anirban; Shriraman, Arrvindh

doi:10.1109/micro.2016.7783752

Cited by 10 publications

(2 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Chainsaw [47] decomposes DAGs into chains instead of trees, which is also a promising alternative as multi-input nodes can also be unfolded as chains. However, the interchain communication, which is frequent for irregular DAGs, happens via a central register file accessed with a bus.…”

Section: Additional Related Workmentioning

confidence: 99%

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

View full text Add to dashboard Cite

A growing number of applications like probabilistic machine learning, sparse linear algebra, robotic navigation, etc., exhibit irregular data flow computation that can be modeled with directed acyclic graphs (DAGs). The irregularity arises from the seemingly random connections of nodes, which makes the DAG structure unsuitable for vectorization on CPU or GPU. Moreover, the nodes usually represent a small number of arithmetic operations that cannot amortize the overhead of launching tasks/kernels for each node, further posing challenges for parallel execution.To enable energy-efficient execution, this work proposes DAG processing unit (DPU) version 2, a specialized processor architecture optimized for irregular DAGs with static connectivity. It consists of a tree-structured datapath for efficient data reuse, a customized banked register file, and interconnects tuned to support irregular register accesses. DPU-v2 is utilized effectively through a targeted compiler that systematically maps operations to the datapath, minimizes register bank conflicts, and avoids pipeline hazards. Finally, a design space exploration identifies the optimal architecture configuration that minimizes the energy-delay product. This hardwaresoftware co-optimization approach results in a speedup of 1.4×, 3.5×, and 14× over a state-of-the-art DAG processor ASIP, a CPU, and a GPU, respectively, while also achieving a lower energy-delay product. In this way, this work takes an important step towards enabling an embedded execution of emerging DAG workloads.

show abstract

Section: Additional Related Workmentioning

confidence: 99%

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

View full text Add to dashboard Cite

show abstract

“…To gain benefit on typical RISC instruction sets, other genres of architectures are developed. One genre incorporates dataflow engines into RISC-based in-order or out-of-order core, uses compilers to find most frequent instruction chunks, and lets the the dataflow engine to execute these chunks to obtain high energy efficiency [13,14,18,19,24,25,34]. As another genre, Forwardflow and Omegaflow are trying to dynamically generate dataflow graphs with pure hardware effort.…”

Section: Dataflow Architecturesmentioning

confidence: 99%

Omegaflow

Zhou

Zhang

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

View full text Add to dashboard Cite

This paper investigates how to better track and deliver dependency in dependency-based cores to exploit instruction-level parallelism (ILP) as much as possible. To this end, we first propose an analytical performance model for state-of-the-art dependency-based core, Forwardflow, and figure out three vital factors affecting its upper bound of performance. Then we propose Omegaflow, a dependencybased architecture adopting three new techniques, which respond to the discovered three factors. Experimental results show that Omegaflow improves IPC by 24.6% compared to the state-of-the-art design, approaching the performance of the OoO architecture with an ideal scheduler (94.4%) without increasing the clock cycle and consumes only 8.82% more energy than Forwardflow. CCS CONCEPTS• Computer systems organization → Superscalar architectures.

show abstract