CFET standard-cell design down to 3Track height for node 3nm and below

Sherazi, Syed Muhammad Yasser; Chae, Jung Kyu; Debacker, Peter; Matti, L.; Verkest, D.; Mocuta, A.; Kim, Ryoung-Han R.; Spessot, A.; Dounde, Amit; Ryckaert, Julien

doi:10.1117/12.2514571

Cited by 10 publications

(12 citation statements)

References 1 publication

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“…Our framework employs a CFET cell architecture and netlist information of [4], [5] and [20], respectively. Fig.…”

Section: B Cfet Cell Architecturementioning

confidence: 99%

“…Recently, feasible CFET-based SDC layouts have been successfully proposed [2], [4], [5]; therefore, CFET has been one of the promising cell structures in sub-7nm and beyond. However, the severe in-cell routing congestion and limited routability at 2.5T demands multi-row CFET SDC architecture to maximize the cell and block-level area benefits [6].…”

Section: Introductionmentioning

confidence: 99%

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Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Cheng

Lee

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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With the relentless scaling of technology nodes, the track number reduction of conventional (Conv.) cell is starting to reach its limitations due to limited routing resources, lateral P-N separations, and performance requirements. As a result, to exploit the benefits of 3D architectures, Complementary-FET (CFET) technology, which stacks P-FET on N-FET or vice versa, is proposed to release the restriction of P-N separation and reduce in-cell routing congestion by enabling P-N direct connections. However, CFET standard cell (SDC) synthesis demands a holistic reconsideration of multi-row structure to maximize the cell and block-level area benefits due to limited in-cell routing tracks and routability that comes from the stacked structure and reduced cell height.In this paper, we propose an SMT (Satisfiability Modulo theories)-based Multi-Row CFET SDC synthesis framework that simultaneously solves place-and-route to minimize the cell area by considering single-row and multi-row placement together. We enable explorations on Upper/Lower M0A/PC routing to leverage the shared-and-split structure across cell rows with the proposed multi-row dynamic complementary pin allocation scheme. We demonstrate that multi-row 2.5T CFET without and with Upper/Lower M0A/PC routing achieve 16.44% and 20.61% on the average reduced cell areas, respectively, compared to 3.5T CFET. Moreover, multi-row 2.5T CFET SDCs achieve 13.43% and 14.40% less block-level area and total wirelength on average compared to 3.5T CFET SDCs.

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“…Our framework employs a CFET cell architecture and netlist information of [4], [5] and [20], respectively. Fig.…”

Section: B Cfet Cell Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Cheng

Lee

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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show abstract

“…Our framework employs a CFET cell architecture and netlist information of [20,22] and [5] , respectively. Figure 3 shows the gridbased placement and routing graph (i.e., Upper/Lower M0A/PC, Abstract Pin Interface (API), MO, Ml, and M2).…”

Section: Cfet Cell Architecturementioning

confidence: 99%

“…Therefore, the access to the MO layer from each pin on the N-FET region (i.e. lower MOA/ PC layer) is restricted to the top or bottom horizontal routing track unless each source/gate/drain pin in P-FET and N-FET that are overlapped on the same vertical track is shared [20,22] 3 . As a result, there exist three kinds of pin shapes according to the sharing status of each pin in stacked FETs as depicted in Figure 1.…”

Section: Cfet Cell Architecturementioning

confidence: 99%

“…Request permissions from permissions@acm.org. ICCAD '20, November 2-5, 2020 Recently, feasible CFET-based SDC layouts are successfully proposed [20,22], therefore CFET has been one of the promising cell structure in sub-7nm or beyond. However, the SDC design in sub-7nm demands holistic exploration (including block-level analysis) in terms of pin-accessibility and routing congestion due to the limited routing resource and exploded conditional design rules of later physical design procedures.…”

Section: Introductionmentioning

confidence: 99%

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A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

Cheng

Lee

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

Thoti,

2023

Nanotechnology

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In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the capability of CTFET under critical dimensions of vertical pitch (n- to p-TFET separation), where it is identified with high scalability. The results of CTFET-inverter show high- noisemargin (NM) and voltage gains compared to the conventional strained-Si GAATFETs at the supply range (VDD) from 0.7 ≥ VDD ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. With better circuit performance, 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

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CFET standard-cell design down to 3Track height for node 3nm and below

Cited by 10 publications

References 1 publication

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

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