Cellular supercomputing with system-on-a-chip

Almási, George; Beece, D.K.; Bellofatto, R.; Bhanot, Gyan; Bickford, R.; Blumrich, Matthias A.; Bright, A. A.; Brunheroto, José R.; Caşcaval, Călin; Castaños, José G.; Ceze, Luís; Cateus, P.; Chatterjee, Siddhartha; Chen, D.; Chiu, George; Cipolla, T.M.; Crumley, P.; Deutsch, A.; Dombrowa, M. B.; Donath, W. E.; Eleftheriou, Maria; Fitch, Blake G.; Gagliano, Joseph A.; Gara, Alan; Germain, Robert S.; Giampapa, Mark; Gupta, Manish; Gustavson, Fred G.; Hall, Shawn A.; Haring, R.A.; Heidel, D.; Heidelberger, Philip; Herger, Lorraine M.; Hoenicke, D.; Jackson, R.D.; Jamaleddine, Tarek J.; Kopcsay, G.V.; Lanzetta, A.P.; Lieber, Derek; Lu, Max; Mendell, M.; Mok, L.; Moreira, José E.; Nathanson, B.J.; Newton, M.; Ohmacht, Martin; Rand, R.; Regan, R.; Sahoo, Ramendra K.; Sanomiya, A.; Schenfeld, Eugen; Singh, S. N.; Song, Peilin; Steinmacher-Burow, Burkhard; Strauß, Karin; Swetz, R.; Takken, Todd; Vranas, P.; Ward, Todd J.; Brown, Jeff; Liebsch, T.; Schram, A.; Ulsh, G.

doi:10.1109/isscc.2002.992189

Cited by 18 publications

(7 citation statements)

References 3 publications

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“…The performance of the coordinate and perspective transformations for case (3)-1 was 100M polygons/s, which was 4.3 times faster than for case (1). Similarly, when the intensity was calculated, the performances for case (3)-1 and (3)-2 were 50 and 67M polygons/s, which were 4.3 and 5.8 times faster, respectively, than for case (1).…”

Section: Methods Of Improving Next-generation Processorsmentioning

confidence: 86%

An Embedded Processor: Is It Ready for High-Performance Computing?

Arakawa

2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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High power-performance ratio is the most important factor in high-performance computing, whose performance is limited by its power budget. A SuperH TM (SH) embedded processor core, SH-X3, implemented in a 90-nm CMOS process running at 600 MHz achieved 1080 Dhrystone MIPS, 4.2 GFLOPS, and 55M polygons/s. Its power performance ratio reaches to as high as 3000 MIPS/W. It is, therefore, a candidate processor for high-performance computing. This paper focuses on the SH processors' low power features, floating-point architecture and performance, and applicability to the highperformance computing.

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Section: Methods Of Improving Next-generation Processorsmentioning

confidence: 86%

An Embedded Processor: Is It Ready for High-Performance Computing?

Arakawa

2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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“…For any configuration, almost all the adders and multipliers are utilized. Many efforts have been made to architect digital CNN [7], [8], [9]; however, only one has been given account on configurability [5]. Our neural network has a simple structure, built from basic modules [10], [11]; therefore, it can be easily implemented on a FPGA chip [12], [13].…”

Section: Cellular Neural Configuration Control Signal S<2>=1mentioning

confidence: 99%

The Configurable Digital Neural Network with Emulated Digital Cellular Neural Network Cores

Zeffer

Hidvégi

2006

2006 IEEE International Conference on Mechatronics

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A configurable Artificial Neuron Network that is neural layers to the higher layers and establishes non-linear capable of establishing both the emulated digital Cellular mapping function between the inputs and the outputs of the Neural Network (CNN) and the static Multilayered network. The reduced structure of the general MFNN is the Feedforward Neural Network (MFNN) is described. The two-layered feedforward neural network shown in Figure 1.

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“…BG/L uses system-on-achip integration [4] and a highly scalable architecture [2] to assemble machines with up-to 65,536 dual-processor compute nodes. The primary communication network of BG/L is a three-dimensional torus.…”

Section: Introductionmentioning

confidence: 99%

Topology Mapping for Blue Gene/L Supercomputer

Chung

Moreira

2006

ACM/IEEE SC 2006 Conference (SC'06)

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Mapping virtual processes onto physical processos is one of the most important issues in parallel computing. The problem of mapping of processes/tasks onto processors is equivalent to the graph embedding problem which has been studied extensively. Although many techniques have been proposed for embeddings of two-dimensional grids, hypercubes, etc., there are few efforts on embeddings of three-dimensional grids and tori. Motivated for better support of task mapping for Blue Gene/L supercomputer, in this paper, we present embedding and integration techniques for the embeddings of three-dimensional grids and tori. The topology mapping library that based on such techniques generates high-quality embeddings of two/three-dimensional grids/tori. In addition, the library is used in BG/L MPI library for scalable support of MPI topology functions. With extensive empirical studies on large scale systems against popular benchmarks and real applications, we demonstrate that the library can significantly improve the communication performance and the scalability of applications.

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Cellular supercomputing with system-on-a-chip

Cited by 18 publications

References 3 publications

An Embedded Processor: Is It Ready for High-Performance Computing?

An Embedded Processor: Is It Ready for High-Performance Computing?

The Configurable Digital Neural Network with Emulated Digital Cellular Neural Network Cores

Topology Mapping for Blue Gene/L Supercomputer

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