Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Posser, Gracieli; Mishra, Vivek; Jain, Pooja; Reis, Ricardo; Sapatnekar, Sachin S.

doi:10.1109/tcad.2015.2456427

Cited by 15 publications

(13 citation statements)

References 11 publications

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“…This is because changing the pin positions affects very marginally the routing. This lifetime improvement is achieved just avoiding the critical output pin positions of the cells [Posser et al 2016], [Posser et al 2014a], [Sapatnekar et al 2015].…”

Section: Resultsmentioning

confidence: 99%

“…are numbered 1 through 7, and the edges of the structure are labeled e 1 through e 6 , as shown in the figure. Since the four PMOS transistors are all identical, by symmetry, the currents injected at nodes 1 and 5 are equal; similarly, the NMOS-injected currents at nodes 3 and 7 are equal [Posser et al 2016].…”

Section: Problem Motivationmentioning

confidence: 99%

“…Due to innovation and importance of this solution it has a patent application [Sapatnekar et al 2015]. Moreover, the novelty and importance of this work can also be seen in a journal publication [Posser et al 2016] and important conferences in the field [Posser et al 2014a], [Posser et al 2014b], [Posser et al 2015c], [Posser et al 2015a] and also a best paper in a regional conference [Posser et al 2015b].…”

Section: Introductionmentioning

confidence: 99%

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Electromigration Aware Cell Design

Posser¹

2016

Anais Do XXIX Concurso De Teses E Dissertações (CTD 2016)

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Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently reducing considerable the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved up to 80.95% by avoiding the critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

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Section: Resultsmentioning

confidence: 99%

Section: Problem Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Electromigration Aware Cell Design

Posser¹

2016

Anais Do XXIX Concurso De Teses E Dissertações (CTD 2016)

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“…Comparing the signal after traversing the two paths indicates whether there has been a transient propagation or not. At the physical level, we can apply different techniques to reduce or avoid problems such as electromigration (Posser et al 2016(Posser et al , 2017. In the example of…”

Section: Reliabilitymentioning

confidence: 99%

“…Changing current density with the change of position of the output pin(Posser et al 2016(Posser et al , 2017 …”

mentioning

confidence: 99%

Internet of Things. Information Processing in an Increasingly Connected World

Strous¹,

Cerf²

2019

IFIP Advances in Information and Communication Technology

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the source, provide a link to the Creative Commons license and indicate if changes were made. The images or other third party material in this book are included in the book's Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the book's Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.

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Strategies for Reducing Power Consumption and Increasing Reliability in IoT

Reis

2019

IFIP Advances in Information and Communication Technology

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The Internet of Things (IoT) demands new challenges in the design of computing and electronics components. One of the challenges is the power reduction of this expanding network of connected devices, where the majority is permanently connected. In a large set of applications, another significant issue is reliability, especially on critical areas as health and transport. This paper shows an overview of design strategies that we have developed to reduce power consumption and to increase reliability in circuits that are components of the IoT, as the reduction of the number of transistors in IoT devices, using optimisation techniques and the physical design of circuits tolerant to radiation effects.

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Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Cited by 15 publications

References 11 publications

Electromigration Aware Cell Design

Electromigration Aware Cell Design

Internet of Things. Information Processing in an Increasingly Connected World

Strategies for Reducing Power Consumption and Increasing Reliability in IoT

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