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The present study successfully demonstrates greener methodology of hydrodynamic cavitation using rotational flows for disinfection of water. Disinfection of two model microbial strainsgram-negative (Escherichia coli) and gram-positive (Staphylococcus aureus) using vortex diode was evaluated. The removal efficacy was quantified for two different cavitation reactors. Practically complete elimination of E. coli was achieved (99%) after 1h of cavitation at a pressure drop of only 0.5 bar. However, elimination of S. aureus using vortex diode was observed to be lower in comparison to the removal of E. coli and only 60% disinfection could be achieved under similar conditions, which can be subsequently enhanced up to 98% by increasing pressure drop. The results were compared with another cavitating device that employs linear flow for cavitation, orifice. The reactor geometry has significant impact on the disinfection process and orifice was found to require significantly higher pressure drop (10 bar) conditions for disinfection and for eliminating gram-positive bacteria with high efficiency. A plausible mechanism for disinfection was proposed to elucidate the role of cavitation in cell destruction leading to death of cells through the rupture of cell wall, oxidative damage and possible DNA denaturation. Also, a cavitation model using per pass disinfection was developed that can provide meaningful physical description of the disinfection process as against the conventional first order reaction rate model. This study would provide meaningful insight into cavitation process based on hydrodynamic cavitation for the destruction of both gram-negative and gram-positive bacteria from various water sources, including industrial wastewaters.

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An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the net's lumped capacitance or the net's effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective "EM" slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the first time, we present a method for incorporating the driver's dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure.

Electromigration (EM) is a traditional reliability concern, aggravated recently due to intense shrinking of wire sizes and the increase in the number of interconnections on a system-on-chip (SoC). Thereby, it challenges the state-of-the-art in design, physics, process and CAD processes. To that regard, we propose a new EM check method named Via Node Vector method. The conventional EM check ignores the lead EM interaction in circuits and only checks the local current densities. The new method addresses the EM interactions and checks the EM reliability at the lead connection sites (called via node). It converts the electrical current density of each lead into an effective current density for the EM interaction consideration. For this, we introduce three new factors: length (F L ), width (F W ), and interaction (F B ). The effective current density divergence at a via node is derived as an addition of the effective current densities of all the interacting leads, which is a close proxy to represent the physical atomic flux divergence at the via node. This divergence at a via node can then be readily compared with the technology EM spec. The proposed method is successfully applied to 28nm node IPs and shows up to ~4X higher safe operating frequency than the conventional method allows. Additionally, it successfully identifies risky sites missed by conventional check. The Via Node Vector Method will provide higher performance with reliability in designing advanced digital and analog circuits.

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