Cell density-driven detailed placement with displacement constraint

Chow, Wing-Kai; Kuang, Jian; He, Xu; Cai, Wenzan; Young, Evangeline F. Y.

doi:10.1145/2560519.2560523

Cited by 40 publications

(13 citation statements)

References 14 publications

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“…Tian et al [20] showed that the size of the SG for a row of P polygons is O((3 4h + 3 2h )P) and it is a very pessimistic upper bound. 5 Because h is a constant for a given cell library, O((3 4h + 3 2h )P) can be treated as O(P). Let p max be the maximum number of polygons in a single cell for the library, and we can say that the space complexity of SG for a cell is O(p max ).…”

Section: A Tpl-aware Single-row Placement With Wsimentioning

confidence: 99%

“…For each cell c i , two nodes g i and fg i , respectively corresponding to the SGs of its layout and flipped layout are introduced in the graph. 5 Due to dummy extension, at most 2h polygons intersect with a cutting line. Thus, in a SG, the number of nodes of a cutting line set and the number of edges between the nodes of two adjacent cutting line sets are bounded by 3 2h and 3 4h , respectively.…”

Section: B Tpl-aware Single-row Placement With Wsi and Cf (Wsi-cf)mentioning

confidence: 99%

“…15(a)], so there is no need to keep them in the graph. By removing these nodes v 5 and v 6 and their adjacent edges (v 5 , v 8 ), (v 5 , v 9 ), (v 1 , v 6 ), and (v 3 , v 6 ), we can find that v 1 , v 3 , v 8 , and v 9 are becoming the ones with no incoming edge and/or outgoing edge so that these nodes and their adjacent edges can also be removed from the graph. Finally, the graph as shown in Fig.…”

Section: Stitch Insertion and Graph Reductionmentioning

confidence: 99%

“…The first three techniques are for intrarow cell movement because they only change the position of a cell or pin in the horizontal direction, while the fourth one is for interrow cell movement because it changes the position of a cell in both horizontal and vertical directions. Note that these four cell movement techniques are often adopted to solve the conventional detailed placement problem that asks for wirelength minimization [5], [10], [12], [13], [15]. A recent work on detailed placement for FinFET process also employs CF and AS to optimize the placement quality [6].…”

Section: Introductionmentioning

confidence: 99%

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On Refining Row-Based Detailed Placement for Triple Patterning Lithography

Chien

Chen

Han

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we study row-based detailed placement refinement for triple patterning lithography (TPL), which asks to find a refined detailed placement solution as well as a valid TPL layout decomposition under the objective of minimizing the number of stitches and the half-perimeter wirelength. Our problem does not have precoloring solutions of cells as the input, and it allows using techniques, including white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, to optimize the solution quality. We first present (resource-constrained) shortest-path-based algorithms for several TPL-aware single-row placement problems that allow or disallow perturbing a given cell ordering. Based on these algorithms, we then propose an approach to our TPL-aware detailed placement refinement problem, which first minimizes the number of stitches and then minimizes the wirelength. Finally, we report extensive experimental results to demonstrate the effectiveness and efficiency of our approach.Index Terms-Detailed placement refinement, layout decomposition, triple patterning lithography (TPL).

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Section: A Tpl-aware Single-row Placement With Wsimentioning

confidence: 99%

Section: B Tpl-aware Single-row Placement With Wsi and Cf (Wsi-cf)mentioning

confidence: 99%

Section: Stitch Insertion and Graph Reductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On Refining Row-Based Detailed Placement for Triple Patterning Lithography

Chien

Chen

Han

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We emphasize that iterative overlap removal helps preserving the timing, differently from a unique legalization step used in related techniques [3,14]. Another strategy would be to perform instant legalization after each movement, as proposed in a recent work that reduces congestion through detailed placement [2]. However, if discrete local search and instant legalization are performed in reverse topological order, the displacement w.r.t.…”

Section: Overlap Removalmentioning

confidence: 99%

Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression

Guth

Livramento

Netto

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

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Timing-driven placement (TDP) finds new legal locations for standard cells so as to minimize timing violations while preserving placement quality. Although violations may arise from unmet setup or hold constraints, most TDP approaches ignore the latter. Besides, most techniques focus on reducing the worst negative slack and let the improvements on total negative slack as a secondary goal. However, to successfully achieve timing closure, techniques must also reduce the total negative slack, which is known as slack histogram compression. This paper proposes a new Lagrangian Relaxation formulation for TDP to compress both late and early slack histograms. To solve the problem, we employ a discrete local search technique that uses the Lagrange multipliers as net-weights, which are dynamically updated using an accurate timing analyzer. To preserve placement quality, our technique uses a small fixed-size window that is anchored in the initial location of a cell. For the experimental evaluation of the proposed technique, we relied on the ICCAD 2014 TDP contest infrastructure. The results show that our technique significantly reduces the timing violations from an initial global placement. On average, late and early total negative slacks are improved by 85.03% and 42.72%, respectively, while the worst slacks are reduced by 71.55% and 34.40%. The overhead in wirelength is less than 0.1%.

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