Stitch aware detailed placement for multiple E-beam lithography

Lin, Yibo; Yu, Bei; Zou, Yi; Li, Zhuo; Alpert, Charles J.; Pan, David Z.

doi:10.1016/j.vlsi.2017.02.004

Cited by 12 publications

(5 citation statements)

References 26 publications

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“…The overall PSR cost is evaluated with the average PSR of all horizontally neighboring cell pairs. From the table, we can see that the congestion refinement is not only effective in removing local congestion, but also smoothing the density, because both PSR and sHPWL are improved by 4% and 1.1% compared with the flow in [33], while no stitch errors occur. Although there is degradation in HPWL, better density and local congestion are more important for routability and final routed wirelength, considering the improvement in sHPWL.…”

Section: Resultsmentioning

confidence: 99%

“…We also evaluate the of local congestion optimization discussed in Problem 2 of Section 3.3 as a post refinement step. Table 4 gives the result comparison between the full flow in [33] and that with our congestion refinement. Since the objective of the refinement is to increase the gap between pairs of cells while minimizing maximum displacement, we introduce a metric called "pair spacing ratio (PSR)" for each pair of horizontally neighboring cells to evaluate the performance,…”

Section: Resultsmentioning

confidence: 99%

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Stitch aware detailed placement for multiple e-beam lithography

Lin

Zou

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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In multiple electron beam lithography (MEBL), a layout is split into stripes and the layout patterns are cut by stripe boundaries, then all the stripes are printed in parallel. If a via pattern or a vertical long wire is overlapping with a stitch, it may suffer from poor printing quality due to the so called stitch error; then the circuit performance may be degraded. In this paper, we propose a comprehensive study on the stitch aware detailed placement to simultaneously minimize the stitch error and optimize traditional objectives, e.g., wirelength and density. Experimental results show that our algorithms are very effective on modified ICCAD 2014 benchmarks that zero stitch error is guaranteed while the scaled half-perimeter wirelength is very comparable to a state-ofthe-art detailed placer. In addition, our technique is very generic that it is applicable to many other placement targets, such as local congestion optimization, which is also demonstrated in the experimental results.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Stitch aware detailed placement for multiple e-beam lithography

Lin

Zou

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…Besides general lithography and MPL aware placement, there are some other researches focusing on emerging technology, like electron beam lithography (EBL), extreme ultra violet (EUV), and Directed Self-Assembly (DSA) [32][33][34][35]. For example, in EBL, due to the application of multiple electron beam lithography (MEBL) for throughput improvement, the features at boundaries of beams are susceptible to stitch errors.…”

Section: Dfm In Placementmentioning

confidence: 99%

“…For example, in EBL, due to the application of multiple electron beam lithography (MEBL) for throughput improvement, the features at boundaries of beams are susceptible to stitch errors. Therefore, it is necessary to avoid features near such regions for better manufacturability, which needs to be considered during both placement [32] and routing [36]. For this problem, Lin et al [32] propose a linear time dynamic programming algorithm for simultaneous optimization on wirelength and stitch errors.…”

Section: Dfm In Placementmentioning

confidence: 99%

“…Therefore, it is necessary to avoid features near such regions for better manufacturability, which needs to be considered during both placement [32] and routing [36]. For this problem, Lin et al [32] propose a linear time dynamic programming algorithm for simultaneous optimization on wirelength and stitch errors. Figure 6 shows the performance of three algorithms in the TPL aware placer proposed by Yu et al [28].…”

Section: Dfm In Placementmentioning

confidence: 99%

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Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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