CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization

Bounceur, Ahcène; Mir, Salvador; Rolindez, L.; Simeu, Emmanuel

doi:10.1007/978-0-387-74909-9_16

Cited by 7 publications

(5 citation statements)

References 13 publications

(23 reference statements)

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“…Using a built-in test technique for an RF LNA as a casestudy, we have shown that the new approach is more accurate than previous approaches, circumventing limitations that arise due to the arbitrary form of the output parameter distributions and the dimensionality of the output space. In addition, this method is very fast and simple to implement and it has been included in an existing mixed-signal/RF Computer-Aided-Test (CAT) platform [20].…”

Section: Discussionmentioning

confidence: 99%

Estimation of Analog Parametric Test Metrics Using Copulas

Bounceur

Mir

Stratigopoulos

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a Built-In-Test (BIT) technique for an RF Low Noise Amplifier (LNA) and to set test limits that result in a desired trade-off between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation.

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Section: Discussionmentioning

confidence: 99%

Estimation of Analog Parametric Test Metrics Using Copulas

Bounceur

Mir

Stratigopoulos

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…They encapsulate tools (e.g., fault extractor or analogue simulator) and facilitate execution of the DOT flow [17] [18]. We use NXP's internal tool DOTSS (defect oriented test simulation system) in this work [19].…”

Section: Previous Workmentioning

confidence: 99%

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Hashempour

Dohmen

Tasic

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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We present an application of Defect Oriented Testing (DOT 1 ) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is already in volume production. A complete flow is presented including defect extraction, defect simulation, test selection, and validation. A major challenge of DOT for mixed signal devices is the simulation time. We address this challenge with a new fault simulation algorithm that provides significant speedup in the DOT process. Based on the fault simulations, we determine a minimal set of tests which detects all defects. The proposed minimal test set is compared with the actual test results of more than a million ICs. We prove that the production tests of the device can be reduced by at least 35%.

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“…. , 6 are computed using the fault simulator developed in [18], [19]. Note that the simulation results obtained in [18] 10 5 ].…”

Section: Case-studymentioning

confidence: 99%

New techniques for selecting test frequencies for linear analog circuits

Bentobache

Bounceur

Euler

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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In this paper we show that the problem of minimizing the number of test frequencies necessary to detect all possible faults in a multi-frequency test approach for linear analog circuits can be modeled as a set covering problem. We will show in particular, that under some conditions on the considered faults, the coefficient matrix of the problem has the strong consecutive-ones property and hence the corresponding set covering problem can be solved in polynomial time. For an efficient solution of the problem, an interval graph formulation is also used and a polynomial algorithm using the interval graph structure is suggested. The optimization of test frequencies for a case-study biquadratic filter is presented for illustration purposes. Numerical simulations with a set of randomly generated problem instances demonstrate two different implementation approaches to solve the optimization problem very fast, with a good time complexity.

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CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization

Cited by 7 publications

References 13 publications

Estimation of Analog Parametric Test Metrics Using Copulas

Estimation of Analog Parametric Test Metrics Using Copulas

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

New techniques for selecting test frequencies for linear analog circuits

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