Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization

Abstract

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on the tradeoff between performance, stability, and power efficiency. In addition to size optimization, physical model parameters including CNT density, CNT diameter, and CNFET flat band voltage are evaluated and optimized for CNFET SRAM performance improvement. Optimized CNFET SRAM is compared with state-of-the-art 7-nm FinFET SRAM cell based on Arizona State University [ASAP 7-nm FinFET predictive technology models (PTM)] library. We find that the read, write EDPs, and static power of the proposed CNFET SRAM cell are improved by 67.6%, 71.5%, and 43.6%, respectively, compared with the FinFET SRAM cell, with slightly better stability. CNT interconnects both inside and in-between CNFET SRAM cells are considered to compose an all-carbon-based SRAM (ACS) array which will be discussed in the Part II of this article. A 7-nm FinFET SRAM cell with copper interconnects is implemented and used for comparison. Index Terms-Carbon nanotube field-effect transistor (CNFET) static random access memory (SRAM) cell, energy-delay-product (EDP), FinFET SRAM cell, read delay, static noise margin (SNM), static power, write delay. I. INTRODUCTIONA S CMOS technology continues to scale down, the supply voltage of integrated circuits (ICs) decreases while the This work was sup-ported in part by the European Commission H2020 CONNECT Project (http://www.connect-h2020.eu/) under Grant 688612 and in part by the Marie Skłodowska-Curie Individual Fellowship under Grant 894805, H-3D-SOC.

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

“…Recently, Chen et al studied the impact of charge transfer doping on the performance and variability of MWCNT interconnects using enhanced compact models [ 53 , 54 ]. They further explored an all-carbon SRAM (ACS) (SRAM: Static Random-Access Memory) using a 5 nm technology node, which showed a great improvement in power efficiency with 72% lower energy-delay-product (EDP) and 48% lower static power, despite a slight speed reduction, compared to 7 nm FinFET (fin field-effect transistor) SRAM cells with copper-based interconnects [ 56 , 66 ].…”

“…Triangle patterns represent the related references [ 23 , 24 ] from left to right respectively. For local level, square patterns represent the related references [ 21 , 22 , 23 , 24 , 38 , 39 , 41 , 53 , 54 , 55 , 56 ], from left to right respectively. Rhombus patterns represent the related references [ 23 , 24 , 39 , 52 ], from left to right respectively.…”

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

“…At fin‐type field‐effect transistor, the gate electrode design creates the gates with autonomous control on top of channel. FinFET Gate width represents “2nh” here n and h specifies number and height of fins respectively 11–14 . The number of fins maximized to have higher on‐current, which creates maximizes the gate control on the channel, which diminish the Short channel effects 15,16 .…”

“…FinFET Gate width represents "2nh" here n and h specifies number and height of fins respectively. [11][12][13][14] The number of fins maximized to have higher on-current, which creates maximizes the gate control on the channel, which diminish the Short channel effects. 15,16 But in SG-FinFET, delay occurs in both read write operation.…”

Characteristic Control of SWCNT-FET by Varying Its Chirality and Dimensions

“…Carbon nanotube field-effect transistors have gained a great importance recently because of their superior electrical, mechanical, and thermal feature [1][2][3][4][5][6][7][8]. The formation of the covalent bonds sp 2 between atoms of carbon results in exceptional mechanical characteristics.…”