Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

Abstract

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

“…The proposed designs take all of the above into consideration to reduce the power consumption by more than 80% in comparison to other designs that employ diodeconnected transistors [12]- [15], [18], [19], [21]- [27]. Also, they reduced the power consumption between 21% and 65% compared to [16], [17], [20], [28], [29] that do not employ diode-connected transistors.…”

“…The authors of [12]- [15] used the traditional designs. They reached ternary outputs by using a Ternary Decoder table, (c) Static power is 2000 times higher, and (d) 98% of the average power consumption is from static power.…”

“…1) The proposed designs do not use standard logic gates, ternary decoders, or ternary encoders, which produce high transistors count and PDP ( [12]- [15], [25], [26]). 2) The proposed designs work on unary operators, which reduces the number of transistors ( [17]- [22], [28], [29]).…”

“…(TDecoder), basic binary gates, and a ternary encoder. In addition, authors of [14], [15] used RRAM with CNTFETs.…”

Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs

“…Designing low-power circuits in nanoscale has been a promising area of research among scientists for a long time. As complementary metal-oxide semiconductor (CMOS) technology reaches its physical limitation [1], several nanotechnologies have been considered to be possible alternatives for CMOS to implement binary and multiple-valued logic circuits [2][3][4][5][6]. One of these nanotechnologies that is expected to provide the implementation of low-power, high-density, and high-speed integrated digital circuits is quantum-dot cellular automata (QCA) [7][8][9][10][11][12].…”