Capacitive physically unclonable function

Kamal, Kamal; Mureşan, Radu

doi:10.1109/ccece.2017.7946730

Cited by 2 publications

(7 citation statements)

References 20 publications

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“…A mixed-signal PUF employs a DAC unit, incorporates analog measurement techniques, and uses an ADC stage to digitize the response. Examples of such PUFs are the integrated circuit identification (ICID) [35]- [37], the silicon nanokey PUF [24], [38], and the C-PUF [25].…”

Section: ) Mixed-signal Pufsmentioning

confidence: 99%

“…• The C-PUF in [25] has square-shaped n-MOSFET capacitors to save the area, whereas the EC-PUF has short-wide n-MOSFET capacitors with a minimum channel length to support attaining more intrinsic variation throughout the fabrication process.…”

Section: G the Ec-puf Variation Aspectsmentioning

confidence: 99%

“…• The two DAC ladders introduced in [25] were based on diffusion N-well resistors. Instead, the EC-PUF ladders were designed using MOSFETs in the subthreshold region as resistors.…”

Section: G the Ec-puf Variation Aspectsmentioning

confidence: 99%

“…The capacitive physically unclonable function (C-PUF) [25] generates its response in such a way that the remote verifier software (VS) can handle the environmentaldriven variations, eliminating the need for the ECC unit.…”

Section: Introductionmentioning

confidence: 99%

“…The C-PUF [25] used square-shaped negative-channel metaloxide-semiconductor field-effect transistor (n-MOSFET) capacitors to reduce the design area; however, such a shape does not lead to the most intrinsic variations throughout the chip manufacturing process. The C-PUF also relied on the internal frequency of the microcontroller, which is usually not high enough to indicate some minute differences among the electronic chips.…”

Section: Introductionmentioning

confidence: 99%

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Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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An electronic physically unclonable function usually includes an on-chip error-correcting code unit, which is vulnerable to security attacks and adds area, power, and data processing time overheads. This paper proposes a mixed-signal physically unclonable function circuit for authentication purposes, which we call the enhanced capacitive physically unclonable function. It divides the input challenge word over multiple computational groups to decrease processing time, increase security, and eliminate the need for error-correcting code units. Most of the challenge bits control capacitive networks grouped into several capacitive cells, while some are analogized through two digital-to-analog converters. One digital-to-analog converter controls the discharge loads of the capacitive cells; the other controls the reference voltage of comparator units. Each comparator controls a counter that digitizes the discharge time into a response chunk. Most of these counters operate at high frequencies for more precise time-to-digital conversion and are overflown to act as roulettes to promote unpredictability. One counter is not overflown to generate a reference response chunk to support error handling. The design allows for more intrinsic variations throughout the fabrication process, leading to unique response chunks. It applies an expanding challenge-response pair approach, generating a 128-bit response word for a 64-bit challenge word. The capacitive nature of the design supports various security features. Simulating the circuit using 45 nm complementary metal-oxide semiconductor technology resulted in an average power of 921.67 µW, a layout area of 22,470 µm 2 , and an average data processing time of 118 µs.

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Section: ) Mixed-signal Pufsmentioning

confidence: 99%

Section: G the Ec-puf Variation Aspectsmentioning

confidence: 99%

“…• The two DAC ladders introduced in [25] were based on diffusion N-well resistors. Instead, the EC-PUF ladders were designed using MOSFETs in the subthreshold region as resistors.…”

Section: G the Ec-puf Variation Aspectsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal

Mureşan

2019

IEEE Access

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Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA

Plusquellic

2022

Cryptography

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Physical unclonable functions (PUFs) are gaining traction as an attractive alternative to generating and storing device keying material over traditional secure non-volatile memory (NVM) technologies. In this paper, we propose an engineered delay-based PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and present an analysis of the statistical quality of its bitstrings using data collected from a set of FPGAs subjected to extended industrial temperature-voltage environmental conditions. The SiRF PUF utilizes the Xilinx shift register primitive and an engineered network of logic gates that are designed to distribute signal paths over a wide region of the FPGA fabric using a MUXing scheme similar in principle to the shift-rows permutation function within the Advanced Encryption Standard algorithm. The shift register is utilized in a unique fashion to enable individual paths through a Xilinx 5-input LUT to be selected as a source of entropy by the challenge. The engineered logic gate network utilizes reconvergent-fanout as a means of adding entropy, eliminating bias and increasing uncertainty with respect to which paths are actually being timed and used in post-processing to produce the secret key or authentication bitstring. The SiRF PUF is a strong PUF build on top of a network with 10’s of millions of possible paths.

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Capacitive physically unclonable function

Cited by 2 publications

References 20 publications

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA

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