CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

Abstract

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single 512 × 128 macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.

MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator

“…In cryptographic computing, the requirement on PIM is different from that of machine learning applications because of its zero tolerance to compute errors. Thus, bit-parallel and bitserial operations are more suitable than the lossy computing mechanisms in current, charge, or voltage domains [17], [18], [19], [20]. Recent Digital in-SRAM architectures [21], [22] have been designed to compute with full precision and high parallelism.…”

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

“…Early IMC attempts [31] employed few Analog to Digital Converters(ADCs) multiplexed across many MACs [17], [22], [31]. The number of ADCs in more recent approaches is higher [24], [27], [42], aiming to maximise speed through parallelism in the computation. As a result of memory folding we get that bit-lines(BL) are multiplexed to data-line(DL), making it so that one MAC is generated per DL at any given time.…”

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

“…Many studies have implemented PIM based on static random-access memory (SRAM) due to its logic compatibility and high operation speed [1][2][3][4][5][6][7]. However, SRAM-based PIMs have the limitations of low bit density and large silicon area [1,2].…”

“…Previous eDRAM structures extended the tention time by employing an additional capacitor in the gain cell. However, the multip accumulate (MAC) operation in an analog PIM usually requires metal-oxide-me (MOM) coupling capacitors [3][4][5], and a sufficiently large capacitor cannot be employ in the gain cell because of the area constraint. In addition, for the same gain cell archit ture, process scaling to the ultra-deep submicron scale further reduces the retention tim As shown in Figure 2, for the same two-transistor (2T) gain cell structure [20,21], simulated retention time decreases by approximately 300 times as the channel length creases from 180 to 28 nm owing to an increased leakage current and a reduced paras capacitance.…”

“…Previous eDRAM structures extended the retention time by employing an additional capacitor in the gain cell. However, the multiplyaccumulate (MAC) operation in an analog PIM usually requires metal-oxide-metal (MOM) coupling capacitors [3][4][5], and a sufficiently large capacitor cannot be employed in the gain cell because of the area constraint. In addition, for the same gain cell architecture, process scaling to the ultra-deep submicron scale further reduces the retention time.…”