Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

Scholz, Mirko; Thijs, S.; Linten, Dimitri; Trémouilles, David; Sawada, M.; Nakaei, T.; Hasebe, T.; Natarajan, M.; Groeseneken, G.

doi:10.1109/eosesd.2007.4401736

Cited by 21 publications

(7 citation statements)

References 3 publications

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“…To study the ESD sensitivity for micromirrors, wafer-level ESD testing was performed on 5 × 5 sized micromirror arrays and individual micromirrors using a wafer-level ESD tester [13]. The human body model (HBM) gives the most commonly used approximation of a real-life ESD event.…”

Section: Wafer Level Hbm Esd Testsmentioning

confidence: 99%

Investigating ESD sensitivity in electrostatic SiGe MEMS

Sangameswaran

Coster

Linten

et al. 2010

J. Micromech. Microeng.

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The sensitivity of electrostatically actuated SiGe microelectromechanical systems to electrostatic discharge events has been investigated in this paper. Torsional micromirrors and RF microelectromechanical systems (MEMS) actuators have been used as two case studies to perform this study. On-wafer electrostatic discharge (ESD) measurement methods, such as the human body model (HBM) and machine model (MM), are discussed. The impact of HBM ESD zap tests on the functionality and behavior of MEMS is explained and the ESD failure levels of MEMS have been verified by failure analysis. It is demonstrated that electrostatic MEMS devices have a high sensitivity to ESD and that it is essential to protect them.

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Section: Wafer Level Hbm Esd Testsmentioning

confidence: 99%

Investigating ESD sensitivity in electrostatic SiGe MEMS

Sangameswaran

Coster

Linten

et al. 2010

J. Micromech. Microeng.

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“…The holding point can be sampled by special instruments, e.g., a wafer-level human body model (HBM) tester [29]. Those testers produce pulses with very slow falling edge transients; during the pulse falling edge, the DUT moves along the quasi-static (QS) trajectory indicated by the blue arrows in Fig.…”

Section: A Transmission Line Pulse Testingmentioning

confidence: 99%

Compact Models for Simulation of On-Chip ESD Protection Networks

Rosenbaum,

Huang,

Drallmeier

et al. 2024

IEEE Trans. Electron Devices

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Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design's ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.

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“…Fig. 8 shows the setup that is used to perform the HBM calibration steps [6]. First, the HBM waveforms from a short load and a resistive load R L (usually 50 Ω) are captured and transformed into the frequency domain.…”

Section: Hbm Testingmentioning

confidence: 99%

“…Fig. 9 shows the schematic of an ESD power clamp consisting of a diode-triggered SCR device [6] and a MOS transistor as gate monitor. Three different SCR variations A, B, and C are used for this study (Table I).…”

Section: Case Study I: Turn-on Of Esd Protection Elementsmentioning

confidence: 99%

ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool?

Scholz

Linten

Thijs

et al. 2009

IEEE Trans. Instrum. Meas.

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The electrical characterization of devices and circuits regarding their electrostatic discharge (ESD) robustness is done by using several measurement tools. Transmission line pulsing (TLP) and human body model (HBM) testing are the commonly used methods. In this paper, TLP and HBM on-wafer setups are presented regarding their electrical schematics, the type of data that is obtained, and the required calibration methodologies. By using three case studies, both test methods are compared by showing their advantages and disadvantages. It is demonstrated that pulsed measurement methods like TLP testing are not always a suitable tool to fully assess the ESD performance of devices or circuits. Index Terms-Electrostatic discharges (ESDs), human body model (HBM), tester calibration, transient and waveforms, transmission line pulsing (TLP).

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Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

Cited by 21 publications

References 3 publications

Investigating ESD sensitivity in electrostatic SiGe MEMS

Investigating ESD sensitivity in electrostatic SiGe MEMS

Compact Models for Simulation of On-Chip ESD Protection Networks

ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool?

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