Current sub-100 nanometer processes employ complex multi-layer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Fullchip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for postlayout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.
The sensitivity of electrostatically actuated SiGe microelectromechanical systems to electrostatic discharge events has been investigated in this paper. Torsional micromirrors and RF microelectromechanical systems (MEMS) actuators have been used as two case studies to perform this study. On-wafer electrostatic discharge (ESD) measurement methods, such as the human body model (HBM) and machine model (MM), are discussed. The impact of HBM ESD zap tests on the functionality and behavior of MEMS is explained and the ESD failure levels of MEMS have been verified by failure analysis. It is demonstrated that electrostatic MEMS devices have a high sensitivity to ESD and that it is essential to protect them.
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