Calculation and application of time-domain waveform sensitivities in asymptotic waveform evaluation

Balivada, Ashok; Holberg, Douglas R.; Pillage, L.T.

doi:10.1109/cicc.1991.164097

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…Exact moment sensitivity computation by this method is an O(MN 2 ) operation. The approximate first-order sensitivity computation for an RC tree by the method described in [5] requires O(MN) time, where M is the number of critical sinks.…”

Section: Moment Sensitivity Computationmentioning

confidence: 99%

“…In [5], a brute-force approach for calculating the delay and slope sensitivities of linear interconnect was proposed. The approach was based on AWE [11] and the AWE time domain sensitivities [5].…”

Section: Introductionmentioning

confidence: 99%

“…The approach was based on AWE [11] and the AWE time domain sensitivities [5]. For each critical fanout node, an AWE-based adjoint analysis technique was used to compute the time-domain voltage sensitivities with respect to the circuit element values.…”

Section: Introductionmentioning

confidence: 99%

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Rc Interconnect Synthesis-a Moment Fitting Approach

Menezes¹,

Pullela²,

Dartu³

et al.

IEEE/ACM International Conference on Computer-Aided Design

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IntroductionAs process technologies are advanced, and integrated circuit feature sizes are reduced, the portion of the path delays attributable to the gates decreases, while the percentage of the delay due to the RC interconnect between gates increases. Most existing algorithms for synthesis and delay optimization, however, do not consider RC interconnect effects, and gate sizing is used to reduce path delays. Such approaches are suboptimal since they ignore the delay reduction possible by interconnect sizing. An optimal design must concurrently size gates and interconnect to optimize delay, signal edge rates, silicon area, metal area, and combinations thereof.Interconnect sizing, which determines the RC delay, has a significant impact on the delay of the gate which drives the interconnect being optimized. Interconnect sizing also affects the delay of subsequent stages since the signal edge rates at the fan-out nodes are strongly dependent on the RC interconnect behavior. The subsequent gate delays are in turn dependent on the slope and shape of the input signals which drive them. For this reason, it is important to optimize the delays as well as the signal slopes at critical fan-out nodes.Signal edge rates also impact the total power dissipation since they control, in part, the rush-through power O MN 2( ) dissipation of the logic gates. Power is even more dependent on the sizing of the gates (which specifies the "resistance" of the transistor path between power and ground) and the total metal area (which specifies the total capacitance, hence the load's energy dissipation per transition). Interconnect, which degrades the signal edge rates between gates, must therefore be considered in the early phases of design from both a delay and a power point of view. In this paper we describe a methodology for RC interconnect synthesis. In contrast to manually designing an RC interconnect by calculating its moments [10], analyzing its delay, and modifying the interconnect repeatedly (a trialand-error procedure) to achieve the target slopes and delays at the fanout nodes of interest, we generate the moments which must yield the required slopes and delays, and then modify the interconnect to fit these moments. Moment sensitivities are used to guide the search for the interconnect wire widths which achieve these objectives. A direct optimization method is used to fine tune the results.

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Section: Moment Sensitivity Computationmentioning

confidence: 99%