Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate

Priority encoder converts multiple binary inputs into binary representation of the index of active input bit with the highest priority. It is used where more than one device want to access the system, it decides the priority of the device to be serve by the system. Priority encoders are used when multiple devices have to share common resources. Several researches are made on these encoders but found no research work on FinFET based Priority encoder. The FinFET device has gained very much attention on recent VLSI designs and FinFET is the substitute for bulk CMOS at nano-scale because of its high short channel effect immunity, scalability and lower leakage power consumption. In this paper, a 4 input-3 output priority encoder is implemented using FinFET design.

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“…36.1 [7]. The tiny slab of undoped silicone perpendicular to the structure is the channel of the FinFET.…”

Section: Finfetmentioning

confidence: 99%

Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

Mishra

Akashe

2015

Springer Proceedings in Physics

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“…The SCEs occur when a fraction of channel escapes gate control due to the influence of junction [6]. Double gate metal oxide semiconductor field effect transistor (DG-MOSFETs) is one of the promising candidate due to its better on-state current and immunity to short channel effects (SCEs) than conventional single gate MOSFETs [7][8][9][10][11]. In sub-10nm regime DG-MOSFETs has good electrostatic gate control over the channel [12].…”

Section: Introductionmentioning

confidence: 99%

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Faisal¹,

Hasan²,

Hossain³

et al. 2017

CCS Archive

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GaN-based double gate metal-oxide semiconductor fieldeffect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green's function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, V GS =1 V while it is going to off at V GS = 0 V. The ON-state and OFFstate drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, V DS = 0.75 V. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (L UN ). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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“…Several innovative multiple gates SOI structures such as Double Gate (DG) MOSFET [1], fully depleted lean channel transistor (DELTA) [2] "Gate All Around"(GAA) MOSFET [3], Pi-gate MOSFET [4] and FinFET [5][6][7][8], have been proposed by various researchers. It is expected that sustained scaling during the next decade will see the complete evolution from the single gate (SG) conventional device to the above mentioned multiple gate MOSFETs (MuGFETs) [9].…”

Section: Introductionmentioning

confidence: 99%

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

Prathima¹,

Bailey²,

Gurumurthy

2012

VLSICS

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A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (I OFF ), while reducing the fin height was beneficial in reducing the gate leakage current (I GATE ). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current

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Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate

Cited by 335 publications

References 1 publication

Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

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