CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

Chen, Guihai; Li, Qing; Muralimanohar,; Ahn, Jung Ho; Brockman,; Jouppi,

doi:10.1109/date.2012.6176428

Cited by 76 publications

(90 citation statements)

References 8 publications

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“…Apart from this, the granularity at which TSVs are placed can be either coarse-or fine-grained, similar to the approach in CACTI-3DD [6]. This granularity defines how many TSVs are placed and what portions of a cache (e.g., peripheral circuits or memory cells) reside on different dies.…”

Section: D Modelmentioning

confidence: 99%

“…A few previous works (e.g., [6]) assume that TSVs in face-to-back are buffered, which may lead to redundant buffering in some designs and also increases the latency and energy overhead of the TSVs. This overhead may be acceptable in large-sized DRAMs that are modeled in CACTI-3DD, but is unacceptable in caches that are relatively smaller in size and becomes increasingly obvious with smaller memory macro designs.…”

Section: D Modelmentioning

confidence: 99%

“…Mamidipaka et al [34] proposed eCACTI, which adds a leakage model into CACTI, and Li et al [35] proposed CACTI-P, which models low-power caches (e.g., cache with sleep transistors). Chen et al [6] presented CACTI-3DD, which adds a TSV model for DRAM memory; however, this tool is designed for DRAM, and hence, does not allow accurate modeling of 3D SRAM caches. 3DCacti [14] provides the ability to model 3D SRAM; however, this tool has not been updated to support technology nodes below 45 nm.…”

Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%

“…As an increasing number of industrial designs utilizes 3D stacking [4,5], research on 3D stacking has become very important. However, existing 3D modeling tools such as CACTI-3DD [6] and 3DCacti [14] do not model NVMs. Another challenge in using multiple tools is that over time, these tools undergo revisions (due to more accurate modeling, bug fixes, etc.)…”

Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%

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DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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Section: D Modelmentioning

confidence: 99%

Section: D Modelmentioning

confidence: 99%

Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%

Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%

See 2 more Smart Citations

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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“…The wire model in CACTI-3DD [56] is used to estimate the 3D DRAM bus delay, where 1 mm wire introduces 0.087 and 0.03 ns delay for TSV at 45-nm process node. As the RC delay is proportional to wire length, the longest route from memory controller across 8 layers to the corner of DRAM layer is around 4.9 mm, thus introduces 0.42 ns delay.…”

Section: Test Environmentsmentioning

confidence: 99%

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems

Liu

Hemani

Paul

et al. 2017

Int J Parallel Prog

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Sequence analysis plays extremely important role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70% of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise sequence alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of 70 mm 2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than corresponding existed hardware accelerator platforms for at least 40 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.

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DRAM-Based Processing-in-Memory

Kim

2012

Processing-in-Memory for AI

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CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

Cited by 76 publications

References 8 publications

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems

DRAM-Based Processing-in-Memory

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