Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that more aggressive branch predictors, especially multiported predictors for multiple branch prediction, may be thermal hot spots, thus further increasing its leakage. Moreover, as the branch predictor holds state that is transient and predictive, elements can be discarded without adverse effect. For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer. Furthermore, the predictive behavior of branch predictors steers them towards decay based not on state-preserving, static storage cells, but rather quasi-static, dynamic storage cells. This paper will examine the results of implementing decaying branch predictor structures with dynamic-appropriately, decaying-cells rather than the standard static SRAM cell.Overall, this paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example. We show decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells which naturally implement decay. More importantly, decay techniques can be applied and should be applied to other such transient and/or predictive structures.

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“…Cache decay, first proposed in [23], [24], aimed to turn off unused portions of caches with long idle times to reduce cache leakage energy.…”

Section: Discussionmentioning

confidence: 99%

Implementing branch-predictor decay using quasi-static memory cells

Juang

Skadron

Martonosi

et al. 2004

ACM Trans. Archit. Code Optim.

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“…There are a number of power-aware architecture designs many of which focus on reducing power of various micro-architectural components [16,17,18,9]. In this section we focus mainly on the FU power reduction techniques [6,10,24].…”

Section: Related Workmentioning

confidence: 99%

“…Techniques have been proposed to reduce static power consumption of various microprocessor components which include Level 1 12 and Level 2 Caches [16,17,18,9] and Functional/Execution Units [10,6,19]. Additional hardware support is needed to reduce static power consumption of various microarchitectural components, which is discussed below.…”

Section: Static Power Reduction Techniquesmentioning

confidence: 99%

Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization

Talli

Srinivasan

Cook

2007

2007 IEEE International Performance, Computing, and Communications Conference

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“…For example, the Alpha 21264 and the StrongARM processors use 30% and 60% of the die area for cache memories [15]. Current efforts at static energy reduction have focused on dynamically resizing active area of caches [5,10,11,18]. In contrast, this paper proposes a technique that statically partitions each set into power-hungry and low-power parts.…”

Section: Introductionmentioning

confidence: 99%

“…Many of techniques [5,10,11,18] proposed to address this problem have focused on cache memory that is a major energy consumer of the entire system because leakage energy is a function of the number of transistors. For example, the Alpha 21264 and the StrongARM processors use 30% and 60% of the die area for cache memories [15].…”

Section: Introductionmentioning

confidence: 99%

Non-uniform Set-Associative Caches for Power-Aware Embedded Processors

Fujii

Sato²

2004

Embedded and Ubiquitous Computing

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Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes a simple technique to reduce the static energy due to subthreshold leakage current. The key idea of our approach is to allow the ways within a cache to be accessed at different speeds and to place infrequently accessed data into the slow ways. We use dual-V t technique to realize the non-uniform setassociative cache, and propose a simple replacement policy to reduce average access latency. Experimental results on 32-way set-associative caches demonstrate that any severe increase in clock cycles to execute application programs is not observed and significant static energy reduction can be achieved, resulting in the improvement of energy-delay 2 product.

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Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

Cited by 14 publications

References 11 publications

Implementing branch-predictor decay using quasi-static memory cells

Implementing branch-predictor decay using quasi-static memory cells

Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization

Non-uniform Set-Associative Caches for Power-Aware Embedded Processors

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