Cache-In-Memory

Abstract

The new technology of Processing-In-Memory now allows relatively large DRAM memory macros to be positioned on the same die with processing logic. Despite the high bandwidth and low latency possible with such macros, more of both is always better. Classical techniques such as caching are typically used for such performance gains, but at the cost of high power. This paper summarizes some recent work into the potential of utilizing structures within such memory macros as cache substitutes, and under what conditions power savings may result. 1 The work described here was performed as part of Mr. Zawodny's M.S. thesis at Notre Dame. He is currently at Goodrich Avionics.