Cache Controller for 4-way Set-Associative Cache Memory

Abstract

This paper presents design of a cache controller for 4-way set associative cache memory and analyzing the performance in terms of cache hit verses miss rates. An FSM based cache controller has been designed for a 4-way set-associative cache memory of 1K byte with block size of 16 bytes. Main memory of 4K byte has been considered. The synthesis has been performed using Xilinx Synthesis Tool (XST) with Virtex-6 FPGA device XC6VLX240T. ISim simulator is used for functional verification of the designed code.The maximum output required time i.e. hold-time after clock is 0.777ns and minimum input time before clock arrival i.e. setup-time for designed module is 1.66ns. The maximum clock frequency is 257.202MHz.The design has also been synthesized in Cadence RTL Compiler tool. Finally, ASIC implementation of the designed cache controller has been done in Cadence Encounter Digital Implementation tool and the GDSII file has been generated.The designed cache controller consumes 5.53mW of total power.

New Content Addressable Memory Architecture for Multi-Core Applications

“…The tested DPCAM has a lower read latency than the tested SA cache; this is because DPCAM compares the incoming tag directly with the stored tag, whereas SA caches must use an index to access the location with a tag to compare to, which increases the latency. Generally, a cache memory based on AM has a latency of around 2 ns for 64 KiB [20], 1.66 ns for AM with 1KiB, and 1.69 ns for 4-way set associative with 2 KiB, which is used in cache controllers [21]. However, the write latency for a cache memory based on AM typically exceeds 2 ns for 64KiB [20].…”

Dual-Port Content Addressable Memory for Cache Memory Applications

“…Thus, they could not be used as shared level of cache in modern multi-core system [12]. There are several works on two approaches to improve memory efficiency by an architectural design [8,[13][14][15] and by efficient cache replacement algorithms [16][17][18][19][20].…”

“…AM architecture using Virtex-6 FPGA series inside the cache controller was presented that was designed to work as a look-up table inside the cache controller with size of 1KiB and a block size of 16 byte [14]. The simulation results show that the cache controller's setup latency is 1.66 ns and total power consumed is 5.53 mW.…”

“…The far-accessing data stored in a line could be overwritten before used. In most cases, the controller can produce far-access operation such that the interested core/s read them from lower level and write them in their private caches [1,14].…”

“…Whereas in DPCAM, the incoming tag is directly compared with the stored tag. Usually, the cache memory based on AM has around 2 ns read latency with the 64 KiB [27], 1.66 ns in AM with 1KiB, and 1.69 ns in 4-way set associative with 2 KiB which is used in cache controller [14]. But write latency for the cache memory based on AM usually exceeds 2 ns for 64KiB [27].…”