Cache consistency in hierarchical-ring-based multiprocessors

Farkas,; Vranesic,; Stumm,

doi:10.1109/superc.1992.236668

Cited by 10 publications

(8 citation statements)

References 13 publications

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“…The Hector multiprocessor [19] [10] recognizes the need for it and specifies a hierarchical cache protocol based upon the broadcasting of requests, as in the snooping protocol used here.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of the slotted ring multiprocessor

Barroso

Dubois

1995

IEEE Trans. Comput.

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As microprocessor speeds continue to improve at a very fast rate the bandwidth requirements for system level interconnections in multiprocessors may eventually rule out the use of shared buses even for small scale multiprocessors. On the other hand high-speed unidirectional links are an emerging technology that has the potential to scale with microprocessor technology and could replace buses as the interconnection fabric for future multiprocessors. In this paper we evaluate the performance of the unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven simulations. We use memory traces from actual execution of parallel programs to drive detailed event-driven simulations of a variety of ring and bus multiprocessors. Snooping and directory coherence protocols for the slotted ring are evaluated in the context of multitasking. Snooping is shown to outperform full-map and linked list directory schemes in the unidirectional slotted ring, and it also compares favorably to high-performance split-transaction bus systems.

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“…The Hector multiprocessor [19] [10] recognizes the need for it and specifies a hierarchical cache protocol based upon the broadcasting of requests, as in the snooping protocol used here.…”

Section: Related Workmentioning

confidence: 99%

Performance evaluation of the slotted ring multiprocessor

Barroso

Dubois

1995

IEEE Trans. Comput.

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“…Even though the initial Hector architecture did not include hardware support for cache coherence (shared data were marked as uncachable), more recent work by Farkas atal [10] recognizes theneed for it and specifies a hierarchical cache protocol based on the broadcasting of requests, as in the snooping protocol used here. Finally, the Kendall Square Reseamh KSR1 [13] is a shared memory multiprocessor commercially available and based on a two-level hierarchy of unidirectional slotted rings with a snooping cache protocol.…”

Section: Related Workmentioning

confidence: 99%

The performance of cache-coherent ring-based multiprocessors

Barroso¹,

Dubois²

1993

Proceedings of the 20th Annual International Symposium on Computer Architecture - ISCA '93

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Advances in circuit and integrationtechnology are continuously boosting the speed of ndcroprocessors. One of the main challenges presented by such developments is the effective use of powerful microprocessors in shared memory multiprocessor configurations.We believe that the interconnection problem is not solved even for small scale shared memory multiprocessors, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new microprocessors.In this paper we evaluate the performance of the unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven simulations. We evaluate both snooping and directory-based coherence protocols for the ring and compare it to high pe~ormance split transaction buses.

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“…Past work has shown that rings are competitive with meshes up to tens of nodes [43][44][45]. Unfortunately, rings suffer from a fundamental scaling problem because a ring's bisection bandwidth does not scale with the number of nodes in the network.…”

Section: Introductionmentioning

confidence: 99%

“…In this chapter, we introduce an approach to construct rings in a hierarchy such that groups of nodes share a simple ring interconnect, and these "local" rings are joined by one or more "global" rings. Figure 1 shows an example of such a hierarchical ring design [23,24,[44][45][46][47][48][49][49][50][51]. Past works [44][45][46][47][48][49][49][50][51] propose hierarchical rings as a scalable alternative to single ring and mesh networks.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control

Ausavarungnirun¹,

Mutlu²

2021

Preprint

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As the number of cores scales to tens and hundreds, the energy consumption of routers across various types of on-chip networks in chip muiltiprocessors (CMPs) increases significantly. A major source of this energy consumption comes from the input buffers inside Network-on-Chip (NoC) routers, which are traditionally designed to maximize performance. To mitigate this high energy cost, many works propose bufferless router designs that utilize deflection routing to resolve port contention. While this approach is able to maintain high performance relative to its buffered counterparts at low network traffic, the bufferless router design suffers performance degradation under high network load.In order to maintain high performance and energy efficiency under both low and high network loads, this chapter discusses critical drawbacks of traditional bufferless designs and describes recent research works focusing on two major modifications to improve the overall performance of the traditional bufferless network-on-chip design. The first modification is a minimally-buffered design that introduces limited buffering inside critical parts of the on-chip network in order to reduce the number of deflections. The second modification is a hierarchical bufferless interconnect design that aims to further improve performance by limiting the number of hops each packet needs to travel while in the network. In both approaches, we discuss design tradeoffs and provide evaluation results based on common CMP configurations with various network topologies to show the effectiveness of each proposal.

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Cache consistency in hierarchical-ring-based multiprocessors

Cited by 10 publications

References 13 publications

Performance evaluation of the slotted ring multiprocessor

Performance evaluation of the slotted ring multiprocessor

The performance of cache-coherent ring-based multiprocessors

Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control

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