Cache-conscious data placement

Calder, Brad; Krintz, Chandra; John, Sonya; Austin, Todd

doi:10.1145/291069.291036

Cited by 162 publications

(31 citation statements)

References 27 publications

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“…The AVC algorithms based on seven different methods of the beam simulation and control algorithms were implemented with a similar specification using the C programming language on a uniprocessor computing domain for similar specification [7] . It is worth mentioning that seven different forms of the AVC algorithm were implemented based on the seven different forms of the beam simulation algorithm.…”

Section: Implementation and Resultsmentioning

confidence: 99%

Real-time design constraints in implementing active vibration control algorithms

Tokhi

2006

Int J Automat Comput

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Section: Implementation and Resultsmentioning

confidence: 99%

Real-time design constraints in implementing active vibration control algorithms

Tokhi

2006

Int J Automat Comput

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“…However, when the code is too complex to be transformed-a situation common in programs that manipulate pointer-based data structures-one must resort to transforming the layout of data structures, improving spatial locality. Many data-layout optimizations have been proposed [3,4,7,8,9,11,15,16,21,23,24], with their specific goals ranging from reordering structure fields [7] to object inlining [11].…”

Section: Introductionmentioning

confidence: 99%

An efficient profile-analysis framework for data-layout optimizations

2002

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Data-layout optimizations rearrange fields within objects, objects within objects, and objects within the heap, with the goal of increasing spatial locality. While the importance of data-layout optimizations has been growing, their deployment has been limited, partly because they lack a unifying framework. We propose a parameterizable framework for data-layout optimization of generalpurpose applications. Acknowledging that finding an optimal layout is not only NP-hard, but also poorly approximable, our framework finds a good layout by searching the space of possible layouts, with the help of profile feedback. The search process iteratively prototypes candidate data layouts, evaluating them by "simulating" the program on a representative trace of memory accesses. To make the search process practical, we develop space-reduction heuristics and optimize the expensive simulation via memoization. Equipped with this iterative approach, we can synthesize layouts that outperform existing non-iterative heuristics, tune application-specific memory allocators, as well as compose multiple data-layout optimizations.

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“…They differ based on: 1) the granularity assumed by the algorithm, and 2) the conflict model used to guide the memory placement. Some of them apply to code [7,10,4,8], while others to data [2,11,3]. In the past, the improvement of cache memory performance was the main issue [7,10,4,2], today we start to see that other kind of memories, such as DRAM, may have a significant role in the optimization of system performance as well [3].…”

Section: Related Workmentioning

confidence: 99%

“…For code placement, procedures and basic blocks are by far the most natural code boundaries which have been considered [7,4]; however, some results refer to more complex code structures such as basic block traces [10] or global control-flow graphs where the procedure boundaries are disregarded [8]. Global variables, arrays and local variables allocated in the program stack are instead the typical objects considered by data placement algorithms [2,11,3]. Different granularities usually refer to different degrees of code or data locality so, depending on the specific program characteristics, all may contribute to improve memory performance.…”

Section: Related Workmentioning

confidence: 99%

“…A quite similar approach is adopted by Gloy et al [4] to represent temporal ordering information among procedures. In [10] a weighted control-flow graph is exploited to select the most frequent sequences of basic blocks; in [3] an access graph is used to grasp the locality properties of a set of variables and, in a quite similar way, it is done by a temporal relationship graph in [2]; finally, a call graph which has been annotated with complex locality constraints on each node is adopted by Zhang et al [11]. With the only exception of the last one, all the reported approaches rely on profiling information which are derived either from frequency profiling or by analyzing the output trace of an instruction-set simulator (ISS).…”

Section: Related Workmentioning

confidence: 99%

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Efficient and effective simulation of memory maps for system-on-chip

Luculli¹

Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.

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The design of complex system-on-chip (SOC) requires new methods and tools for the optimization of embedded software which is executed on ever more complex hardware architectures. The tuning of the memory subsystem is particularly difficult due to the many design parameters which are involved and the long time which is required to simulate different design configurations. In this paper, we propose a very effective mechanism for the simulation of generic memory maps on architectures with instruction and/or data cache memory. An important characteristic of our implementation is its large flexibility: any memory map and any cache configuration can be simulated without the need to modify or to re-compile the application code. We implemented such mechanism in our ISA retargetable environment and we showed that it loosely impacts the simulation performance.

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Cache-conscious data placement

Cited by 162 publications

References 27 publications

Real-time design constraints in implementing active vibration control algorithms

Real-time design constraints in implementing active vibration control algorithms

An efficient profile-analysis framework for data-layout optimizations

Efficient and effective simulation of memory maps for system-on-chip

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