An efficient profile-analysis framework for data-layout optimizations

RubinShai,; BodikRastislav,; ChilimbiTrishul,

doi:10.1145/565816.503287

Cited by 64 publications

(47 citation statements)

References 32 publications

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“…In a broader perspective, we note that the recent years have seen substantial work in using compressed traces for profile-driven analysis [10], deciding data layout [18], program optimization and debugging [24]. This paper demonstrates another application of compressed traces, specifically for embedded processor design.…”

Section: Discussionmentioning

confidence: 92%

“…The compression algorithm used to generate our trace is lossless; thus our simulation results are exact. We note that simulation of a compressed trace for a single cache configuration has been reported in [18]. There are several differences between [18] and our work: (a) we simulate multiple cache configurations in a single pass, (b) unlike our work, the technique of [18] is restricted to fully associative caches, and (c) our work employs customized memory management techniques (see Section 4.3) to achieve scalability; on the other hand, the work of [18] mentions practical difficulties in simulating large caches.…”

Section: Related Workmentioning

confidence: 99%

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Design space exploration of caches using compressed traces

Negi

Mitra

et al. 2004

Proceedings of the 18th Annual International Conference on Supercomputing

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Memory subsystem, in particular, cache design is important for both high performance and embedded computing systems. The trend towards increased customization for embedded systems, in addition, requires the design of an optimal cache configuration for each application. Trace driven simulation is widely used to evaluate cache performance. However, traces are storage inefficient and simulation is too slow especially when hundreds of design points need to be evaluated. Trace based simulation has two sources of redundancies: multiple occurrences of the same sequence in the trace and containment relationship among cache configurations. We exploit both the redundancies in a unified manner by simulating multiple cache configurations in a single pass directly over a compressed trace (which has already identified the repetitive sequences). Experimental results indicate that our approach achieves significant savings both in storage and in simulation time compared to existing methods.

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Section: Discussionmentioning

confidence: 92%

Section: Related Workmentioning

confidence: 99%

Design space exploration of caches using compressed traces

Negi

Mitra

et al. 2004

Proceedings of the 18th Annual International Conference on Supercomputing

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“…When the correct profile itself either cannot be generated or is not known, researchers have used causality analysis to assess if their profile is actionable [Mytkowicz et al, 2010, Rubin et al, 2002]. …”

Section: Background and Related Workmentioning

confidence: 99%

AOT vs. JIT: impact of profile data on code quality

Wade¹

2017

SIGPLAN Not.

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Dynamic or just-in-time (JIT) compilation can generate optimized native code during each program run, and is a popular technique used by process-level virtual machines (VM) to simultaneously achieve binary code portability and high execution performance. JIT compilers typically collect profile information at run-time to guide selective compilation and profile-guided optimizations (PGO). Ahead-of-time (AOT) compilation is an alternative model that can also achieve portability by converting the distributed binary to native code when the software is first installed. The AOT compilation model removes the overhead of online profile collection and dynamic compilation, and may reduce VM complexity. However, AOT compilation cannot customize the generated native code to different program inputs/behaviors. The goal of this work is to investigate and quantify the implications of the AOT compilation model on the quality of the generated native code for current VMs. To achieve our goal, this study develops and conducts many new innovative experiments using a variety of novel frameworks. First, we quantify the quality of native code generated by the two compilation models for a state-of-the-art (HotSpot) Java VM. Second, we determine how the amount of profile data collected affects the quality of generated code. Third, we develop a mechanism to determine the similarity or representative-ness of different profile data for a given program run for guiding PGOs.Fourth, we investigate how the accuracy of profile data affects its ability to effectively guide PGOs. Finally, we categorize the profile data types in our VM and explore the contribution of each such category to performance.iii

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“…These data reorganization techniques improve the overall I/O performance due to a prior knowledge of application I/O behaviors. Besides, data partition [22][23] and replication [11] [16] techniques are also widely used either to reduce disk head movements or to increase the degree of I/O parallelism. For example, Zhang et al [16] proposed a data replication scheme to amortize I/O workloads with multiple replicas to improve the performance, so that each file server only serves requests from one or a limited number of processes.…”

Section: B Layout Optimizationmentioning

confidence: 99%

A Server-Level Adaptive Data Layout Strategy for Parallel File Systems

Song

Jin

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Abstract-Parallel file systems are widely used for providing a high degree of I/O parallelism to mask the gap between I/O and memory speed. However, peak I/O performance is rarely attained due to complex data access patterns of applications. Based on the observation that the I/O performance of small requests is often limited by the request service rate, and the performance of large requests is limited by I/O bandwidth, we take into consideration both factors and propose a server-level adaptive data layout strategy. The proposed strategy adopts different stripe sizes for different file servers according to the data access characteristics on each individual server. We let the file servers that can fully utilize bandwidth hold more data, and the file servers that are limited with request service rate hold less data. As a result, heavy-load servers can offload some data accesses to light-load servers for potential improvement of I/O performance. We present a method to measure access cost for each data block and then utilize an equal-depth histogram approach to distributed data blocks across multiple servers adaptively, so as to balance data accesses on all file servers. Analytical and experimental results demonstrate that the proposed server-level adaptive layout strategy can improve I/O performance by as much as 80.3% and is more appropriate for applications with complex data access patterns.Keywords-Server-level adaptive data layout, variable stripe size, equal-depth histogram, data layout optimization, parallel file system

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An efficient profile-analysis framework for data-layout optimizations

Cited by 64 publications

References 32 publications

Design space exploration of caches using compressed traces

Design space exploration of caches using compressed traces

AOT vs. JIT: impact of profile data on code quality

A Server-Level Adaptive Data Layout Strategy for Parallel File Systems

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