Cache- and register-aware system reliability evaluation based on data lifetime analysis

Kooli, Maha; Kaddachi, Firas; Natale, Giorgio Di; Bosio, Alberto

doi:10.1109/vts.2016.7477299

Cited by 10 publications

(4 citation statements)

References 18 publications

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“…As Figure 4 highlights, faults could propagate through the different hardware structures composing the full system. However, it could happen that they are masked during the propagation either at the technological or at the architectural level [42]. When a fault reaches the soft-…”

Section: Fault Injectormentioning

confidence: 99%

Investigating data representation for efficient and reliable Convolutional Neural Networks

Ruospo

Sánchez

Traiola

et al. 2021

Microprocessors and Microsystems

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Section: Fault Injectormentioning

confidence: 99%

Investigating data representation for efficient and reliable Convolutional Neural Networks

Ruospo

Sánchez

Traiola

et al. 2021

Microprocessors and Microsystems

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“…While the previous techniques perform the analysis on a real processor, our approach uses the VISA of LLVM, which makes the evaluation less dependent from the hardware architecture. Using the same VISA, Kooli et al [15] use the lifetime analysis to compute the minimum percentage of failure probability of faults occurring in the data (RAM, data cache). Compared to this technique, the proposed approach computes the exact failure probability, and is able to target faults occurring in both data and instructions.…”

Section: B Analytical Reliability Evaluation Techniquesmentioning

confidence: 99%

Cache-aware reliability evaluation through LLVM-based analysis and fault injection

Kooli

Natale

Bosio

2016

2016 IEEE 22nd International Symposium on on-Line Testing and Robust System Design (IOLTS)

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1-Reliability evaluation is a high costly process that is mainly carried out through fault injection or by means of analytical techniques. While the analytical techniques are fast but inaccurate, the fault injection is more accurate but extremely time consuming. This paper presents an hybrid approach combining analytical and fault injection techniques in order to evaluate the reliability of a computing system, by considering errors that affect both the data and the instruction cache. Compared to existing techniques, instead of targeting the hardware model of the cache (e.g., VHDL description), we only consider the running application (i.e., the software layer). The proposed approach is based on the Low-Level Virtual Machine (LLVM) framework coupled with a cache emulator. As input, the tool requires the application source code, the cache size and policy, and the target microprocessor instruction set. The main advantage of the proposed approach is the achieved speed up quantified in magnitude orders compared to existing fault injection techniques. For the validation, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of the approach.

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“…It is necessary to evaluate the reliability of programs under the influence of soft errors. Moreover, the results of reliability analysis are useful for improving the error detection mechanisms [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

“…Lu et al [22] proposed an empirical model to predict the SDC proneness of a program's data called SDCTune, which is based on static and dynamic features of the program extracted by performing fault injection experiments on a small set of benchmark programs. Kooli et al [3] used the concept of the variable lifetime and the variable residence to compute the percentage of masked faults in the RAM, data cache, and register files. G. Li et al [16] built a crash model based on the dynamic dependency graph and proposed an algorithm to analyze the propagation of given soft errors that have an impact on the program outputs, and to predict crashes on GPGPU.…”

Section: Introductionmentioning

confidence: 99%

Reliability Analysis for Programs with Redundancy Computation for Soft Errors

Meng

Zhang

Xue

et al. 2023

J. Phys.: Conf. Ser.

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Soft error is one of the factors which may affect the reliability of computer programs. A common method to alleviate the impact of soft errors is redundancy computation, a classical data flow error detection mechanism. However, a program with redundancy computation may still have some vulnerable spots, which might be caused by the flaw during implementation or the instruction reordering given by compiler optimization. Finding the vulnerable spots of a program with redundancy computation is of great significance to evaluate the capability of the error detection mechanism. There are some conventional methods to analyze the reliability of a program under soft errors, such as the irradiation experiment, fault injection, and modeling analysis. However, the irradiation experiment is expensive, fault injection is very time-consuming, and the existing modeling analysis methods have not considered the error detection mechanism. This paper proposes a novel method of reliability analysis for programs with redundancy computation by analyzing the dynamic instruction sequence. Experimental results show that our approach has fairly high accuracy and a false negative rate of about 0.0545.

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Cache- and register-aware system reliability evaluation based on data lifetime analysis

Cited by 10 publications

References 18 publications

Investigating data representation for efficient and reliable Convolutional Neural Networks

Investigating data representation for efficient and reliable Convolutional Neural Networks

Cache-aware reliability evaluation through LLVM-based analysis and fault injection

Reliability Analysis for Programs with Redundancy Computation for Soft Errors

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