C-Exact Hypergraphs in Concurrency and Sequentiality Analyses of Cyber-Physical Systems Specified by Safe Petri Nets

Wiśniewski, Remigiusz; Wiśniewska, M.; Jarnut, Marcin

doi:10.1109/access.2019.2893284

Cited by 23 publications

(23 citation statements)

References 45 publications

(56 reference statements)

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“…Pursuing our assessment, we measured that the three methods of Hippo took, respectively, 65 seconds, 25 min, and 1 hour 53 min to process the collection of benchmarks. The Hippo portal uses a timeout of nearly 22-minutes, since, for five of the models, [28] reports that decomposition using hypergraphs takes more than one hour. Actually, the three methods could process, respectively, 70.5%, 92.5%, and 91.1% of the collection.…”

Section: Experiments Resultsmentioning

confidence: 99%

“…5], and the distribution of a Petri net to geographical locations [5,11]. On the algorithmic side, one can mention decomposition methods that compute a coverage of a net by strongly connected state machines, e.g., [12], approaches based on invariants and semiflows, e.g., [3,21,24], and approaches based on reachability analysis, some using concurrency graphs on which decomposition can be expressed as a graph colouring algorithm [27], others using hypergraphs, which seem more compact that concurrency graphs [28]. On the software implementation side, one can mention the Diane tool [19], which seems no longer accessible today, and the Hippo tool, which is developed at the University of Zielona Góra (Poland) and available on-line through a dedicated web portal 1 .…”

Section: Introductionmentioning

confidence: 99%

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Automatic Decomposition of Petri Nets into Automata Networks – A Synthetic Account

Bouvier

Garavel

León

2020

Lecture Notes in Computer Science

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This article revisits the problem of decomposing a Petri net into a network of automata, a problem that has been around since the early 70s. We reformulate this problem as the transformation of an ordinary, one-safe Petri net into a flat, unit-safe NUPN (Nested-Unit Petri Net) and define a quality criterion based on the number of bits required for the structural encoding of markings. We propose various transformation methods, all of which we implemented in a tool chain that combines NUPN tools with third-party software, such as SAT solvers, SMT solvers, and tools for graph colouring and finding maximal cliques. We perform an extensive evaluation of these methods on a collection of more than 12,000 nets from diverse sources, including nets whose marking graph is too large for being explored exhaustively.

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Section: Experiments Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automatic Decomposition of Petri Nets into Automata Networks – A Synthetic Account

Bouvier

Garavel

León

2020

Lecture Notes in Computer Science

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“…It can be seen that technology mapping considers sharing of PAL-based blocks using a graph of outputs. As a result, the obtained structure was reduced by three blocks compared with the basic number of blocks (1).…”

Section: Graph Of Outputs In the Process Of Synthesis Of Combinationamentioning

confidence: 99%

“…This enables the implementation of more complex functionalities, and above all, provides flexibility without degrading the dynamic properties of the solutions obtained. In general, programmable devices are closely related to CPS, as exemplified by Petri nets [1][2][3]. This layer should be characterized by considerable flexibility of some properties [4] including the implementation of some tasks in a software manner [5].…”

Section: Introductionmentioning

confidence: 99%

Graph of Outputs in the Process of Synthesis Directed at CPLDs

Kubica¹,

Kania²

2019

Mathematics

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The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

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“…There are various specification techniques of control processes [ 10 ], including Petri nets (PN) [ 11 , 12 , 13 ], statecharts [ 14 ] and diagrams of the Unified Modelling Language (UML) [ 15 , 16 ]. There are also some approaches to using these specification techniques in the domain of cyber-physical systems, such as [ 17 , 18 , 19 , 20 , 21 , 22 , 23 ]. Each specification technique has its advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Formal Verification of Control Modules in Cyber-Physical Systems

Grobelna

2020

Sensors

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The paper proposes a novel formal verification method for a state-based control module of a cyber-physical system. The initial specification in the form of user-friendly UML state machine diagrams is written as an abstract rule-based logical model. The logical model is then used both for formal verification using the model checking technique and for prototype implementation in FPGA devices. The model is automatically transformed into a verifiable model in nuXmv format and into synthesizable code in VHDL language, which ensures that the resulting models are consistent with each other. It also allows the early detection of any errors related to the specification. A case study of a manufacturing automation system is presented to illustrate the approach.

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C-Exact Hypergraphs in Concurrency and Sequentiality Analyses of Cyber-Physical Systems Specified by Safe Petri Nets

Cited by 23 publications

References 45 publications

Automatic Decomposition of Petri Nets into Automata Networks – A Synthetic Account

Automatic Decomposition of Petri Nets into Automata Networks – A Synthetic Account

Graph of Outputs in the Process of Synthesis Directed at CPLDs

Formal Verification of Control Modules in Cyber-Physical Systems

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