Bundled execution of recurring traces for energy-efficient general purpose processing

Gupta, Shantanu; Feng, Shuguang; Ansari, Amin; Mahlke, Scott; August, David I.

doi:10.1145/2155620.2155623

Cited by 95 publications

(59 citation statements)

References 33 publications

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“…Hardware acceleration exists in many forms, such as analog accelerators [6,50], static [13,19,28,38,43,52,55] and dynamic datapath accelerators [14,25,27], and programmable accelerators, such as GPUs and DSPs. In this work, we focus on static datapath accelerators.…”

Section: Background and Motivationmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

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Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.

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Section: Background and Motivationmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

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show abstract

“…5.7.8. Core Area Like previous approaches that propose heterogeneous designs (e.g., [57,23,29]), HBA optimizes for a heavily energy/power-constrained future, targeting designs in which energy and power are performance limiters [16]. Also like other heterogeneous designs that attempt to reduce power/energy through increased specialization, the power benefits of HBA come at the cost of additional chip area.…”

Section: Block Info Cachementioning

confidence: 99%

“…Several prior works combine a "cold pipeline" and "hot pipeline" that execute infrequent (cold) and frequent (hot) code traces respectively [46,8,23]. PARROT [46] captures hot code traces and performs optimizations on them to produce code for an optimized VLIW engine.…”

Section: Related Workmentioning

confidence: 99%

“…PARROT [46] captures hot code traces and performs optimizations on them to produce code for an optimized VLIW engine. Gupta et al propose BERET [23], which adds an auxiliary co-processor that executes data-flow subgraphs for hot code when those subgraphs fit in the coprocessor. These designs are superficially similar to the use of VLIW backends in HBA.…”

Section: Related Workmentioning

confidence: 99%

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The heterogeneous block architecture

Fallin¹,

Wilkerson

Mutlu³

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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This paper makes two new observations that lead to a new heterogeneous core design. First, we observe that most serial code exhibits fine-grained heterogeneity: at the scale of tens or hundreds of instructions, regions of code fit different microarchitectures better (at the same point or at different points in time). Second, we observe that by grouping contiguous regions of instructions into blocks that are executed atomically, a core can exploit this heterogeneity: atomicity allows each block to be executed independently on its own execution backend that fits its characteristics best.Based on these observations, we propose a fine-grained heterogeneous design that combines heterogeneous execution backends into one core. Our core design, the heterogeneous block architecture (HBA), breaks the program into blocks of code, determines the best backend for each block, and specializes the block for that backend. As an initial, concrete design, we combine out-of-order, VLIW, and in-order backends, using simple heuristics to choose backends. We compare HBA to multiple baseline core designs (including monolithic out-of-order, clustered out-of-order, in-order and a state-of-the-art heterogeneous core design) and show that HBA can provide significantly better energy efficiency than all designs at similar performance. Averaged across 184 traces from a wide variety of workloads, HBA reduces core power by 36.4% and energy per instruction by 31.9% compared to a 4-wide out-of-order core. We conclude that HBA provides a flexible substrate for exploiting fine-grained heterogeneity, enabling new energy-performance tradeoff points in core design.

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“…Recent work has proposed on-chip accelerators for energy efficiency (dark silicon) in the context of general-purpose (i.e., desktop and mobile) workloads [12,13,14,28,32]. While these proposals try to improve the efficiency of the memory hierarchy, the applicability of the proposed techniques to big data workloads is limited due to the deep software stacks and vast datasets in today's server applications.…”

Section: Related Workmentioning

confidence: 99%

Meet the walkers

Kocberber¹,

Grot

Picorel³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

150

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The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance and ushered an era of power-limited chips. These developments motivate the design of DBMS accelerators that (a) maximize utility by accelerating the dominant operations, and (b) provide flexibility in the choice of DBMS, data layout, and data types.We study data analytics workloads on contemporary inmemory databases and find hash index lookups to be the largest single contributor to the overall execution time. The critical path in hash index lookups consists of ALU-intensive key hashing followed by pointer chasing through a node list. Based on these observations, we introduce Widx, an on-chip accelerator for database hash index lookups, which achieves both high performance and flexibility by (1) decoupling key hashing from the list traversal, and (2) processing multiple keys in parallel on a set of programmable walker units. Widx reduces design cost and complexity through its tight integration with a conventional core, thus eliminating the need for a dedicated TLB and cache. An evaluation of Widx on a set of modern data analytics workloads (TPC-H, TPC-DS) using full-system simulation shows an average speedup of 3.1x over an aggressive OoO core on bulk hash table operations, while reducing the OoO core energy by 83%.

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Bundled execution of recurring traces for energy-efficient general purpose processing

Cited by 95 publications

References 33 publications

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

The heterogeneous block architecture

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