Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)

Stroud, Charles E.; Konala, S.; Chen, Ping; Abramovici, M.

doi:10.1109/vtest.1996.510883

Cited by 133 publications

(43 citation statements)

References 4 publications

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“…FPGAs with support for memory and partial memory readback allow a test strategy similar to scan design where the response is captured in sequential elements, read back, and finally analyzed [20,21]. The readback increases the time for test.…”

Section: State Of the Art Fpga Testmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing.In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

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Section: State Of the Art Fpga Testmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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“…BIST and BISR methods for detecting and handling faults have been used extensively in memory designs [9], [11], [12], as well as in FPGA's in an off-line manner [13]- [19]. The FPGA BIST techniques mainly focus on reconfiguring the entire FPGA into set states in order to identify and then locate faults.…”

Section: Related Workmentioning

confidence: 99%

On-line fault detection for bus-based field programmable gate arrays

Shnidman

Mangione-Smith

Potkonjak

1998

IEEE Trans. VLSI Syst.

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Abstract-We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA's). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system. Index Terms-Digital system fault tolerance, field programmable gate arryas, self-testing.

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“…A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing [11], which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs.…”

Section: Introductionmentioning

confidence: 99%