An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing

Alaghi,; Yarandi,; Navabi,

doi:10.1109/ats.2006.261034

Cited by 6 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There has been considerable work carried out on application independent testing of logic blocks of the FPGA [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The basic idea of BIST based approach presented in [4][5][6][7] is to program all the logic blocks of the FPGA so that some of them work as test pattern generator [TPG], some work as output response analyzer [ORA] while other LUTs are subjected to test.…”

Section: Prevous Workmentioning

confidence: 99%

“…On the other hand, application-dependent test involves testing of only the logic and routing resources which are used in a design implementation. There are several BIST methods have been used for testing the FPGAs for both application dependent and independent testing [4,5,6,7,9,13,14,15]. All these methods assume that some LUTs under test are fault free as they are used in the design of test pattern generator and output response analyzer.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fault propagation and diagnosis of LUTs in an FPGA without fault free assumptions

Kumar

2010

2010 International Conference on Electronic Devices, Systems and Applications

View full text Add to dashboard Cite

This paper proposes a new technique for propagating and diagnosing the faulty LUTs in an FPGA. This technique uses flip-flops and multiplexers for the fault propagation rather than LUTs and therefore the fault free assumption of the LUTs is eliminated. Also this technique diagnosis location of the multiple faulty LUTs precisely thus avoiding any fault masking. This method has been tested on the commercial FPGA and the experimental results are provided.

show abstract

Section: Prevous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault propagation and diagnosis of LUTs in an FPGA without fault free assumptions

Kumar

2010

2010 International Conference on Electronic Devices, Systems and Applications

View full text Add to dashboard Cite

show abstract

“…Different methodologies for application-dependent testing have been presented in literature for logic block testing or interconnect testing or both [1,2,4,[6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. These testing methodologies are able to not only detect faults within the FPGA chip but also diagnose the actual location of the faults [1,5,8,10,12,16,[20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Nirmalraj

Radhakrishnan

Pandiyan

2021

IET Computers & Digital Tech

View full text Add to dashboard Cite

Fault detection and diagnosis of a Field-Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck-at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair-wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS'89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is log 2where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by log 2 ðn þ 2Þ when compared with previously published methods available in the literature.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

show abstract

“…Testing of LUTs is a mature field [20] [21] [22] and recent developments have considered timing performance as well as stuck-at faults. [23] and [24] have both proposed methods for analysing the propagation delays of logic chains.…”

Section: 2mentioning

confidence: 99%

Fault tolerant methods for reliability in FPGAs

Stott

Sedcole

Cheung

2008

2008 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

Reliability and process variability are serious issues for FPGAs in the future. Fortunately FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome some of these issues. This paper provides the first comprehensive survey of fault detection methods and fault tolerance schemes specifically for FPGAs, with the goal of laying a strong foundation for future research in this field. All methods and schemes are qualitatively compared and some particularly promising approaches highlighted.

show abstract

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing

Abstract: This paper presents a BIST architecture for FPGA Look-Up

Cited by 6 publications

References 12 publications

Fault propagation and diagnosis of LUTs in an FPGA without fault free assumptions

Fault propagation and diagnosis of LUTs in an FPGA without fault free assumptions

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Fault tolerant methods for reliability in FPGAs

Contact Info

Product

Resources

About