Built-in self-test of FPGA interconnect

Stroud, Charles E.; Wijesuriya, Sajith; Hamilton, C.; Abramovici, M.

doi:10.1109/test.1998.743180

Cited by 130 publications

(63 citation statements)

References 12 publications

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“…For testing interconnect, stuck-on and stuck-open faults in programmable interconnect points and stuck-at and bridge faults for wires [13,14] are targeted. Tests for delay faults have been introduced in [15].…”

Section: State Of the Art Fpga Testmentioning

confidence: 99%

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Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing.In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

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Section: State Of the Art Fpga Testmentioning

confidence: 99%

“…While the programmable interconnect structures are to some extent already tested during the test of other structures, dedicated deterministic testing based on multiple test configurations has been proposed [14,22]. Due to the complexity of the interconnect configuration circuitry, a very high number of TCs is required.…”

Section: State Of the Art Fpga Testmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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“…Multiple fault detection is not guaranteed in [11] due to the use of XOR trees and D flip-flop (DFF) chains to propagate the test outputs. The first BIST proposal for testing interconnects resources is a comparisonbased approach by Stroud et al [10]. They configure a subset of wire segments and PSs to form two groups of wires under test (WUTs).…”

Section: Previous Workmentioning

confidence: 99%

Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs

S¹,

Agrawal²

2012

IJCA

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Field programmable gate arrays (FPGAs) are the reconfigurable logic devices which are widely used in many applications like system prototyping, complex computing systems, automotive electronics and mobile devices. FPGAs have become very popular at present because of their features like high logic capacity, reconfigurability and regular structure with less area cost. However, increase in density and complexity also has resulted in more probability of defects. FPGAs are prone to different types of faults similar to other complicated integrated circuit chips. Faults may occur due to many reasons like environmental conditions or aging of the device. The rate of occurrence of permanent faults can be quite high in emerging technologies, and hence there is a need for periodic testing of such FPGAs. To effectively deal with the increased defect density, we need efficient methods for fault detection and correction.Here, we present an approach for testing FPGA interconnect that exploits the reprogramability of an FPGA to create builtin self test (BIST) logic by configuring it only during off-line testing. In this way, testability is achieved without any area overhead, since the BIST logic "disappears" when the circuit is reconfigured for its normal system operation. We have used XILINX ISE12.1 for simulation and synthesis.

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“…But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable [10].…”

Section: Introductionmentioning

confidence: 99%